linux-kernel - Re: [PATCH 06/12] perf_events: implement PERF_SAMPLE

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1317923665.29658.18.camel@twins>
Date:	Thu, 06 Oct 2011 19:54:24 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	Stephane Eranian <eranian@...gle.com>
Cc:	linux-kernel@...r.kernel.org, mingo@...e.hu, acme@...hat.com,
	ming.m.lin@...el.com, andi@...stfloor.org, robert.richter@....com,
	ravitillo@....gov
Subject: Re: [PATCH 06/12] perf_events: implement PERF_SAMPLE_BRANCH for
 Intel X86

On Thu, 2011-10-06 at 16:49 +0200, Stephane Eranian wrote:
> @@ -876,6 +889,13 @@ static void intel_pmu_disable_event(struct perf_event *event)
>                 return;
>         }
>  
> +       /*
> +        * must disable before any actual event
> +        * because any event may be combined with LBR
> +        */
> +       if (intel_pmu_needs_lbr_smpl(event))
> +               intel_pmu_lbr_disable(event);
> +
>         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
>                 intel_pmu_disable_fixed(hwc);
>                 return; 

I don't get that, since until you disable the counter a PMI could happen
(*) you'd need to disable the LBR after you disable the counters.

* doesn't actually happen since we likely have the whole pmu disabled
here, but that's another thing ;-)
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/