[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <4E8D3B9D.6030208@dsn.lapis-semi.com>
Date: Thu, 06 Oct 2011 14:24:45 +0900
From: Tomoya MORINAGA <tomoya-linux@....lapis-semi.com>
To: Toshiharu Okada <toshiharu-linux@....okisemi.com>
CC: grant.likely@...retlab.ca, spi-devel-general@...ts.sourceforge.net,
linux-kernel@...r.kernel.org, qi.wang@...el.com,
yong.y.wang@...el.com, joel.clark@...el.com,
kok.howg.ewe@...el.com, tomoya-linux@....okisemi.com
Subject: Re: [PATCH] spi_topcliff_pch: supports a spi mode setup and bit order
setup by IO control
Hi Grant,
It seems this patch Toshiharu posted in 20-July remains not to be
reviewed by you.
Could you review this patch and merge to your tree ?
Thanks in advance,
--
tomoya
ROHM Co., Ltd.
(2011/07/20 14:56), Toshiharu Okada wrote:
> This patch supports a spi mode setup and bit order setup by IO control.
> spi mode: mode 0 to mode 3
> bit order: LSB first, MSB first
>
> Signed-off-by: Toshiharu Okada<toshiharu-linux@....okisemi.com>
> ---
> drivers/spi/spi_topcliff_pch.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
> index 79e48d4..dec83c9 100644
> --- a/drivers/spi/spi_topcliff_pch.c
> +++ b/drivers/spi/spi_topcliff_pch.c
> @@ -1038,6 +1038,7 @@ static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> master->num_chipselect = PCH_MAX_CS;
> master->setup = pch_spi_setup;
> master->transfer = pch_spi_transfer;
> + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
> dev_dbg(&pdev->dev,
> "%s transfer member of SPI master initialized\n", __func__);
>
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists