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Message-ID: <20111011110728.13004b1c@lxorguk.ukuu.org.uk> Date: Tue, 11 Oct 2011 11:07:28 +0100 From: Alan Cox <alan@...rguk.ukuu.org.uk> To: Ming Lei <tom.leiming@...il.com> Cc: "Rafael J. Wysocki" <rjw@...k.pl>, mark gross <mgross@...ux.intel.com>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, Linux PM List <linux-pm@...r.kernel.org> Subject: Re: [Question] PM-QoS: PM_QOS_CPU_DMA_LATENCY == interrupt latency? > > No. Well it may be on some platforms but it isn't the same thing. On some > > devices a DMA transfer doesn't need the CPU involved but needs the CPU to > > respond within a set timescale (eg for coherency or bus arbitration). It > > I understand only the CPU can respond after it is notified by a > interrupt event, don't I? The instruction stream being executed maybe, but not things like the cache > Also could you give a example about how the CPU responds to a DMA transfer > within a set timescale if it is required? The kind of thing you are dealing with is DMA engine requests a cache line of data CPU wakes out of sleep, completes bus transaction CPU goes back to sleep DMA engine starts outputting data bits over SPI bus or similar repeat until done so it's not instruction level stuff, merely bus traffic. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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