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Message-ID: <20111103075929.7084a9b8@jbarnes-desktop>
Date: Thu, 3 Nov 2011 07:59:29 -0700
From: Jesse Barnes <jbarnes@...tuousgeek.org>
To: "Michael S. Tsirkin" <mst@...hat.com>
Cc: Rusty Russell <rusty@...tcorp.com.au>,
Sasha Levin <levinsasha928@...il.com>,
Linus Torvalds <torvalds@...ux-foundation.org>,
lkml - Kernel Mailing List <linux-kernel@...r.kernel.org>,
Alexey Kardashevskiy <aik@...abs.ru>,
Amit Shah <amit.shah@...hat.com>,
Christian Borntraeger <borntraeger@...ibm.com>,
Krishna Kumar <krkumar2@...ibm.com>,
Pawel Moll <pawel.moll@....com>,
Wang Sheng-Hui <shhuiw@...il.com>,
virtualization@...ts.linux-foundation.org, kvm@...r.kernel.org
Subject: Re: [PATCH RFC] virtio-pci: flexible configuration layout
On Thu, 3 Nov 2011 01:31:11 +0200
"Michael S. Tsirkin" <mst@...hat.com> wrote:
> Add a flexible mechanism to specify virtio configuration layout, using
> pci vendor-specific capability. A separate capability is used for each
> of common, device specific and data-path accesses.
>
> Warning: compiled only.
> This patch also needs to be split up, pci_iomap changes
> also need arch updates for non-x86.
>
> We also will need to update the spec.
>
> See the first chunk for layout documentation.
>
> Posting here for early feedback.
>
> In particular:
>
> Do we need to require offset to be aligned?
> Does iowrite16 work with unaligned accesses on all architectures?
> Does using ioread/write as we do add overhead as compared to
> plain PIO accesses?
>
> Jesse - are you OK with the pci_iomap_range API proposed here
> (see last chunks)?
> I noticed lots of architectures duplicate the implementation
> of pci_iomap - makes sense to clean that up?
Probably makes sense to have a weak version at least for arches that
just do the same thing. But some arches really do need separate
versions because they wrap read/write as well...
Given the arch constraints, it's probably not possible to get rid of
the min/max args in favor of a simple offset/len pair like we have for
ioremap. But if we could that would be even better.
--
Jesse Barnes, Intel Open Source Technology Center
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