/*
 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
 */

#ifndef ML7213_IOH_I2S
#define ML7213_IOH_I2S

#define I2S_AEMPTY_THRESH	64	/* Almost  Empty Threshold */
#define I2S_AFULL_THRESH	64	/* Almost  Full Threshold */

#define MAX_I2S_RX_CH	MAX_I2S_CH
#define MAX_I2S_TX_CH	MAX_I2S_CH

#define	INTER_BUFF_SIZE		(I2S_AEMPTY_THRESH*4 \
				 *I2S_DMA_SG_NUM \
				 *I2S_DMA_SG_MAX)
#define	I2S_DMA_SG_NUM		(128)
#define	I2S_DMA_SG_MAX		(64)

struct ioh_i2s_data;


enum ioh_direction {
	IOH_PLAYBACK = 0,
	IOH_CAPTURE,
};

enum ioh_i2s_fifo_type {
	IOH_FIFO_32  = 4,
	IOH_FIFO_16 = 2,
	IOH_FIFO_8 = 1,
};

enum ioh_i2s_status {
	IOH_EOK = 0,
	IOH_EDONE = 1,
	IOH_EUNDERRUN = 2,
	IOH_EOVERRUN = 3,
	IOH_EFRAMESYNC = 4,
};

struct ioh_i2s_config_common_reg {
	u32 i2sclkcnt;	/*clock control register(ch0~5) */
	u32 i2sistatus;	/*interrupt status */
	u32 i2sidisp;		/*active interrupts */
	u32 i2simask;		/*interrupt mask */
	u32 i2simaskclr;	/*interrupt mask clear */
};

struct ioh_i2s_config_tx_reg {
	u32 i2sdrtx;	/*data register */
	u32 i2scnttx; /*control register */
	u32 i2sfifoctx;	/*FIFO control register */
	u32 i2saftx;	/*almost full threshold setting */
	u32 i2saetx;	/*almost empty threshold setting */
	u32 i2smsktx;	/*interrupt mask settings */
	u32 i2sisttx;	/*for acknowledging interrupts */
	u32 i2smontx;	/*monitor register */
};

struct ioh_i2s_config_rx_reg {
	u32 i2sdrrx;	/* data register */
	u32 i2scntrx;	/* control register */
	u32 i2sfifocrx;/* FIFO control register */
	u32 i2safrx;	/* almost full threshold setting */
	u32 i2saerx;	/* almost empty threshold setting */
	u32 i2smskrx;	/* interrupt mask settings */
	u32 i2sistrx;	/* for acknowledging interrupts */
	u32 i2smonrx;	/* monitor register */
};

struct ioh_i2s_config_reg {
	/* The common register settings */
	struct ioh_i2s_config_common_reg cmn;

	/* TX channel settings */
	struct ioh_i2s_config_tx_reg tx;

	/* RX channel settings */
	struct ioh_i2s_config_rx_reg rx;
};

/* For power management save/retore use */
struct ioh_i2s_pm_common_reg {
	u32 i2sclkcnt[6];
	u32 i2simask;
};

struct ioh_i2s_pm_ch_reg {
	u32 i2sdrtx;	/* Tx: data register */
	u32 i2scnttx; /* Tx: control register */
	u32 i2sfifoctx;	/* Tx: FIFO control register */
	u32 i2saftx;	/* Tx: almost full threshold setting */
	u32 i2saetx;	/* Tx: almost empty threshold setting */
	u32 i2smsktx;	/* Tx: interrupt mask settings */
	u32 i2sisttx;	/* Tx: for acknowledging interrupts */
	u32 i2scntrx;	/* Rx: control register */
	u32 i2sfifocrx; /* Rx: FIFO control register */
	u32 i2safrx;	/* Rx: almost full threshold setting */
	u32 i2saerx;	/* Rx: almost empty threshold setting */
	u32 i2smskrx;	/* Rx: interrupt mask settings */
	u32 i2sistrx;	/* Rx: for acknowledging interrupts */
};

#endif