/* * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. */ #ifndef ML7213_IOH_I2S_CONFIG #define ML7213_IOH_I2S_CONFIG #include "ioh_i2s.h" #define IOH_I2S_USE_PARAM (1) #define I2S_SUPPORT_FS_NUM (7) #define PERIOD_POS_MAX (I2S_DMA_SG_NUM) #define PERIOD_LEN_TX (I2S_AEMPTY_THRESH * PERIOD_POS_MAX) #define PERIOD_LEN_RX (I2S_AFULL_THRESH * PERIOD_POS_MAX) #define SUPPORT_FORMAT (SNDRV_PCM_FMTBIT_U8 | \ SNDRV_PCM_FMTBIT_S16_LE | \ SNDRV_PCM_FMTBIT_S32_LE) #define MAX_PERIOD_SIZE_TX (PERIOD_LEN_TX*4) #define MAX_PERIOD_SIZE_RX (PERIOD_LEN_RX*4) #if (PERIOD_LEN_TX < (I2S_AEMPTY_THRESH*I2S_DMA_SG_NUM)) #error IOH_I2S_CONFIG Error : PERIOD_LEN_TX is enlarged more. #endif #if (PERIOD_LEN_RX < (I2S_AFULL_THRESH*I2S_DMA_SG_NUM)) #error IOH_I2S_CONFIG Error : PERIOD_LEN_RX is enlarged more. #endif /* ######################################################################## */ /* ### Parameter setup possible value ### */ /* ######################################################################## */ /* ioh_mssel_t */ #define ioh_mssel_slave (0) #define ioh_mssel_master (1) enum ioh_bclkpol_t { ioh_bclkpol_falling = 0, ioh_bclkpol_rising, }; enum ioh_masterclksel_t { ioh_masterclksel_mclk = 0, ioh_masterclksel_mlbclk, }; enum ioh_lrckfmt_t { ioh_lrclkfmt_i2s = 1, ioh_lrclkfmt_longframe, ioh_lrclkfmt_shortframe, }; enum ioh_mclkfs_t { ioh_mclkfs_64fs = 0, ioh_mclkfs_128fs, ioh_mclkfs_192fs, ioh_mclkfs_256fs, ioh_mclkfs_384fs, ioh_mclkfs_512fs, ioh_mclkfs_768fs, ioh_mclkfs_1024fs, }; /* ioh_dabit_t */ #define ioh_dabit_8bit (0) #define ioh_dabit_16bit (2) #define ioh_dabit_24bit (5) /* ioh_bclkfs_t */ #define ioh_bclkfs_8fs (0) #define ioh_bclkfs_16fs (1) #define ioh_bclkfs_32fs (2) #define ioh_bclkfs_64fs (3) /* ioh_tel_t */ #define ioh_tel_i2s_fmt (0) #define ioh_tel_tel_fmt (1) enum ioh_dlyoff_t { ioh_dlyoff_dly_on = 0, /* date delat on */ ioh_dlyoff_dly_off, /* date delat off */ }; /* ioh_lsb_t */ #define ioh_lsb_msb_first (0) #define ioh_lsb_lsb_first (1) enum ioh_lrpol_t { ioh_lrpol_no_invert = 0, /* Low of LRCLK is L data. High of LRCLK is R data. */ ioh_lrpol_invert, /* Low of LRCLK is R data. High of LRCLK is L data. */ }; enum ioh_aft_t { ioh_aft_front = 0, ioh_aft_back, }; struct i2s_config_tab_t { unsigned int i2sclkcnt; unsigned int i2scnttx; unsigned int i2scntrx; unsigned int i2s_mclk; }; struct i2s_config_rate_sub_t { unsigned int rate; unsigned int mclkfs; }; struct i2s_config_rate_t { struct i2s_config_rate_sub_t i2s_config_rate_sub[I2S_SUPPORT_FS_NUM]; }; /* ######################################################################## */ /* ### Parameter Config PreProcessor ### */ /* ######################################################################## */ /* I2S Config Value */ #define USE_CHANNELS_MIN 1 #define USE_CHANNELS_MAX 2 #define MAX_I2S_CH 6 /*I2S0 ~ I2S5*/ /* =================== I2S CH0 config =================== */ #define I2S_CH0_MCLK (12288000) /* Master Clock Frequency[Hz] */ #if IOH_I2S_USE_PARAM #define I2S_CH0_FS_16000 16000 #define I2S_CH0_FS_32000 32000 #define I2S_CH0_FS_48000 48000 #else #define I2S_CH0_FS_8000 8000 #define I2S_CH0_FS_11025 11025 #define I2S_CH0_FS_22050 22050 #define I2S_CH0_FS_44100 44100 #endif /* select master or slave. The value is ioh_mssel_t */ #define I2S_CH0_MSSEL (ioh_mssel_master) /* select MCLK or MLBCLK into Master Clock. The value is enum ioh_masterclk_t */ #define I2S_CH0_MASTERCLKSEL (ioh_masterclksel_mclk) /* I2S CH0 stereo config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH0_BCLKPOL_STEREO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH0_LRCKFMT_STEREO (ioh_lrclkfmt_i2s) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH0_TX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH0_TX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of TX side. The value is ioh_lrpol_t */ #define I2S_CH0_TX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of TX side. The value is ioh_aft_t */ #define I2S_CH0_TX_AFT_STEREO (ioh_aft_front) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH0_RX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH0_RX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of RX side. The value is ioh_lrpol_t */ #define I2S_CH0_RX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of RX side. The value is ioh_aft_t */ #define I2S_CH0_RX_AFT_STEREO (ioh_aft_front) /* I2S CH0 monaural config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH0_BCLKPOL_MONO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH0_LRCKFMT_MONO (ioh_lrclkfmt_longframe) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH0_TX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH0_TX_LSB_MONO (ioh_lsb_msb_first) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH0_RX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH0_RX_LSB_MONO (ioh_lsb_msb_first) /* =================== I2S CH1 config =================== */ #define I2S_CH1_MCLK (12288000) /* Master Clock Frequency[Hz] */ #if IOH_I2S_USE_PARAM #define I2S_CH1_FS_16000 16000 #define I2S_CH1_FS_32000 32000 #define I2S_CH1_FS_48000 48000 #else #define I2S_CH1_FS_8000 8000 #define I2S_CH1_FS_11025 11025 #define I2S_CH1_FS_22050 22050 #define I2S_CH1_FS_44100 44100 #endif /* select master or slave. The value is ioh_mssel_t */ #define I2S_CH1_MSSEL (ioh_mssel_master) /* select MCLK or MLBCLK into Master Clock. The value is enum ioh_masterclk_t */ #define I2S_CH1_MASTERCLKSEL (ioh_masterclksel_mclk) /* I2S CH1 stereo config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH1_BCLKPOL_STEREO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH1_LRCKFMT_STEREO (ioh_lrclkfmt_i2s) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH1_TX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH1_TX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of TX side. The value is ioh_lrpol_t */ #define I2S_CH1_TX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of TX side. The value is ioh_aft_t */ #define I2S_CH1_TX_AFT_STEREO (ioh_aft_front) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH1_RX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH1_RX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of RX side. The value is ioh_lrpol_t */ #define I2S_CH1_RX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of RX side. The value is ioh_aft_t */ #define I2S_CH1_RX_AFT_STEREO (ioh_aft_front) /* I2S CH1 monaural config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH1_BCLKPOL_MONO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH1_LRCKFMT_MONO (ioh_lrclkfmt_longframe) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH1_TX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH1_TX_LSB_MONO (ioh_lsb_msb_first) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH1_RX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH1_RX_LSB_MONO (ioh_lsb_msb_first) /* =================== I2S CH2 config =================== */ #define I2S_CH2_MCLK (12288000) /* Master Clock Frequency[Hz] */ #if IOH_I2S_USE_PARAM #define I2S_CH2_FS_16000 16000 #define I2S_CH2_FS_32000 32000 #define I2S_CH2_FS_48000 48000 #else #define I2S_CH2_FS_8000 8000 #define I2S_CH2_FS_11025 11025 #define I2S_CH2_FS_22050 22050 #define I2S_CH2_FS_44100 44100 #endif /* select master or slave. The value is ioh_mssel_t */ #define I2S_CH2_MSSEL (ioh_mssel_master) /* select MCLK or MLBCLK into Master Clock. The value is enum ioh_masterclk_t */ #define I2S_CH2_MASTERCLKSEL (ioh_masterclksel_mclk) /* I2S CH2 stereo config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH2_BCLKPOL_STEREO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH2_LRCKFMT_STEREO (ioh_lrclkfmt_i2s) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH2_TX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH2_TX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of TX side. The value is ioh_lrpol_t */ #define I2S_CH2_TX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of TX side. The value is ioh_aft_t */ #define I2S_CH2_TX_AFT_STEREO (ioh_aft_front) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH2_RX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH2_RX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of RX side. The value is ioh_lrpol_t */ #define I2S_CH2_RX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of RX side. The value is ioh_aft_t */ #define I2S_CH2_RX_AFT_STEREO (ioh_aft_front) /* I2S CH2 monaural config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH2_BCLKPOL_MONO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH2_LRCKFMT_MONO (ioh_lrclkfmt_longframe) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH2_TX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH2_TX_LSB_MONO (ioh_lsb_msb_first) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH2_RX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH2_RX_LSB_MONO (ioh_lsb_msb_first) /* =================== I2S CH3 config =================== */ #define I2S_CH3_MCLK (12288000) /* Master Clock Frequency[Hz] */ #if IOH_I2S_USE_PARAM #define I2S_CH3_FS_16000 16000 #define I2S_CH3_FS_32000 32000 #define I2S_CH3_FS_48000 48000 #else #define I2S_CH3_FS_8000 8000 #define I2S_CH3_FS_11025 11025 #define I2S_CH3_FS_22050 22050 #define I2S_CH3_FS_44100 44100 #endif /* select master or slave. The value is ioh_mssel_t */ #define I2S_CH3_MSSEL (ioh_mssel_master) /* select MCLK or MLBCLK into Master Clock. The value is enum ioh_masterclk_t */ #define I2S_CH3_MASTERCLKSEL (ioh_masterclksel_mclk) /* I2S CH3 stereo config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH3_BCLKPOL_STEREO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH3_LRCKFMT_STEREO (ioh_lrclkfmt_i2s) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH3_TX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH3_TX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of TX side. The value is ioh_lrpol_t */ #define I2S_CH3_TX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of TX side. The value is ioh_aft_t */ #define I2S_CH3_TX_AFT_STEREO (ioh_aft_front) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH3_RX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH3_RX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of RX side. The value is ioh_lrpol_t */ #define I2S_CH3_RX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of RX side. The value is ioh_aft_t */ #define I2S_CH3_RX_AFT_STEREO (ioh_aft_front) /* I2S CH3 monaural config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH3_BCLKPOL_MONO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH3_LRCKFMT_MONO (ioh_lrclkfmt_longframe) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH3_TX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH3_TX_LSB_MONO (ioh_lsb_msb_first) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH3_RX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH3_RX_LSB_MONO (ioh_lsb_msb_first) /* =================== I2S CH4 config =================== */ #define I2S_CH4_MCLK (12288000) /* Master Clock Frequency[Hz] */ #if IOH_I2S_USE_PARAM #define I2S_CH4_FS_16000 16000 #define I2S_CH4_FS_32000 32000 #define I2S_CH4_FS_48000 48000 #else #define I2S_CH4_FS_8000 8000 #define I2S_CH4_FS_11025 11025 #define I2S_CH4_FS_22050 22050 #define I2S_CH4_FS_44100 44100 #endif /* select master or slave. The value is ioh_mssel_t */ #define I2S_CH4_MSSEL (ioh_mssel_master) /* select MCLK or MLBCLK into Master Clock. The value is enum ioh_masterclk_t */ #define I2S_CH4_MASTERCLKSEL (ioh_masterclksel_mclk) /* I2S CH4 stereo config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH4_BCLKPOL_STEREO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH4_LRCKFMT_STEREO (ioh_lrclkfmt_i2s) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH4_TX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH4_TX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of TX side. The value is ioh_lrpol_t */ #define I2S_CH4_TX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of TX side. The value is ioh_aft_t */ #define I2S_CH4_TX_AFT_STEREO (ioh_aft_front) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH4_RX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH4_RX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of RX side. The value is ioh_lrpol_t */ #define I2S_CH4_RX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of RX side. The value is ioh_aft_t */ #define I2S_CH4_RX_AFT_STEREO (ioh_aft_front) /* I2S CH4 monaural config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH4_BCLKPOL_MONO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH4_LRCKFMT_MONO (ioh_lrclkfmt_longframe) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH4_TX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH4_TX_LSB_MONO (ioh_lsb_msb_first) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH4_RX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH4_RX_LSB_MONO (ioh_lsb_msb_first) /* =================== I2S CH5 config =================== */ #define I2S_CH5_MCLK (12288000) /* Master Clock Frequency[Hz] */ #if IOH_I2S_USE_PARAM #define I2S_CH5_FS_16000 16000 #define I2S_CH5_FS_32000 32000 #define I2S_CH5_FS_48000 48000 #else #define I2S_CH5_FS_8000 8000 #define I2S_CH5_FS_11025 11025 #define I2S_CH5_FS_22050 22050 #define I2S_CH5_FS_44100 44100 #endif /* select master or slave. The value is ioh_mssel_t */ #define I2S_CH5_MSSEL (ioh_mssel_master) /* select MCLK or MLBCLK into Master Clock. The value is enum ioh_masterclk_t */ #define I2S_CH5_MASTERCLKSEL (ioh_masterclksel_mclk) /* I2S CH5 stereo config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH5_BCLKPOL_STEREO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH5_LRCKFMT_STEREO (ioh_lrclkfmt_i2s) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH5_TX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH5_TX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of TX side. The value is ioh_lrpol_t */ #define I2S_CH5_TX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of TX side. The value is ioh_aft_t */ #define I2S_CH5_TX_AFT_STEREO (ioh_aft_front) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH5_RX_DLYOFF_STEREO (ioh_dlyoff_dly_on) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH5_RX_LSB_STEREO (ioh_lsb_msb_first) /* select LRCLK polarity of RX side. The value is ioh_lrpol_t */ #define I2S_CH5_RX_LRPOL_STEREO (ioh_lrpol_no_invert) /* select transmit data front or back of RX side. The value is ioh_aft_t */ #define I2S_CH5_RX_AFT_STEREO (ioh_aft_front) /* I2S CH5 monaural config */ /* select BCLK polarity. The value is enum ioh_bclkpol_t */ #define I2S_CH5_BCLKPOL_MONO (ioh_bclkpol_falling) /* select DAI format. The value is enum ioh_lrckfmt_t */ #define I2S_CH5_LRCKFMT_MONO (ioh_lrclkfmt_longframe) /* select TX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH5_TX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select TX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH5_TX_LSB_MONO (ioh_lsb_msb_first) /* select RX data delay on or off. The value is enum ioh_dlyoff_t */ #define I2S_CH5_RX_DLYOFF_MONO (ioh_dlyoff_dly_off) /* select RX data format LSB or MSB first. The value is ioh_lsb_t */ #define I2S_CH5_RX_LSB_MONO (ioh_lsb_msb_first) /* ######################################################################## */ /* ### Parameter Check PreProcessor ### */ /* ######################################################################## */ /* ===== CH0 Parameter Error Check ==== */ #define USE_RATE_MAX_CH0 (0) #ifdef I2S_CH0_FS_8000 #define USE_RATE_CH0_8000 SNDRV_PCM_RATE_8000 #define USE_RATE_MIN_CH0 (8000) #if (USE_RATE_MAX_CH0 < 8000) #undef USE_RATE_MAX_CH0 #define USE_RATE_MAX_CH0 (8000) #endif #else #define USE_RATE_CH0_8000 0 #endif #ifdef I2S_CH0_FS_11025 #define USE_RATE_CH0_11025 SNDRV_PCM_RATE_11025 #ifndef USE_RATE_MIN_CH0 #define USE_RATE_MIN_CH0 (11025) #endif #if (USE_RATE_MAX_CH0 < 11025) #undef USE_RATE_MAX_CH0 #define USE_RATE_MAX_CH0 (11025) #endif #else #define USE_RATE_CH0_11025 0 #endif #ifdef I2S_CH0_FS_16000 #define USE_RATE_CH0_16000 SNDRV_PCM_RATE_16000 #ifndef USE_RATE_MIN_CH0 #define USE_RATE_MIN_CH0 (16000) #endif #if (USE_RATE_MAX_CH0 < 16000) #undef USE_RATE_MAX_CH0 #define USE_RATE_MAX_CH0 (16000) #endif #else #define USE_RATE_CH0_16000 0 #endif #ifdef I2S_CH0_FS_22050 #define USE_RATE_CH0_22050 SNDRV_PCM_RATE_22050 #ifndef USE_RATE_MIN_CH0 #define USE_RATE_MIN_CH0 (22050) #endif #if (USE_RATE_MAX_CH0 < 22050) #undef USE_RATE_MAX_CH0 #define USE_RATE_MAX_CH0 (22050) #endif #else #define USE_RATE_CH0_22050 0 #endif #ifdef I2S_CH0_FS_32000 #define USE_RATE_CH0_32000 SNDRV_PCM_RATE_32000 #ifndef USE_RATE_MIN_CH0 #define USE_RATE_MIN_CH0 (32000) #endif #if (USE_RATE_MAX_CH0 < 32000) #undef USE_RATE_MAX_CH0 #define USE_RATE_MAX_CH0 (32000) #endif #else #define USE_RATE_CH0_32000 0 #endif #ifdef I2S_CH0_FS_44100 #define USE_RATE_CH0_44100 SNDRV_PCM_RATE_44100 #ifndef USE_RATE_MIN_CH0 #define USE_RATE_MIN_CH0 (44100) #endif #if (USE_RATE_MAX_CH0 < 44100) #undef USE_RATE_MAX_CH0 #define USE_RATE_MAX_CH0 (44100) #endif #else #define USE_RATE_CH0_44100 0 #endif #ifdef I2S_CH0_FS_48000 #define USE_RATE_CH0_48000 SNDRV_PCM_RATE_48000 #ifndef USE_RATE_MIN_CH0 #define USE_RATE_MIN_CH0 (48000) #endif #if (USE_RATE_MAX_CH0 < 48000) #undef USE_RATE_MAX_CH0 #define USE_RATE_MAX_CH0 (48000) #endif #else #define USE_RATE_CH0_48000 0 #endif #define USE_RATE_CH0 (USE_RATE_CH0_8000|USE_RATE_CH0_11025 | \ USE_RATE_CH0_16000|USE_RATE_CH0_22050 | \ USE_RATE_CH0_32000|USE_RATE_CH0_44100 | \ USE_RATE_CH0_48000) #define I2S_CH0_64FS (I2S_CH0_MCLK/64) #define I2S_CH0_128FS (I2S_CH0_MCLK/128) #define I2S_CH0_192FS (I2S_CH0_MCLK/192) #define I2S_CH0_256FS (I2S_CH0_MCLK/256) #define I2S_CH0_384FS (I2S_CH0_MCLK/384) #define I2S_CH0_512FS (I2S_CH0_MCLK/512) #define I2S_CH0_768FS (I2S_CH0_MCLK/768) #define I2S_CH0_1024FS (I2S_CH0_MCLK/1024) #if (I2S_CH0_MSSEL == ioh_mssel_master) #ifdef I2S_CH0_FS_8000 #if (I2S_CH0_64FS != I2S_CH0_FS_8000) && \ (I2S_CH0_128FS != I2S_CH0_FS_8000) && \ (I2S_CH0_192FS != I2S_CH0_FS_8000) && \ (I2S_CH0_256FS != I2S_CH0_FS_8000) && \ (I2S_CH0_384FS != I2S_CH0_FS_8000) && \ (I2S_CH0_512FS != I2S_CH0_FS_8000) && \ (I2S_CH0_768FS != I2S_CH0_FS_8000) && \ (I2S_CH0_1024FS != I2S_CH0_FS_8000) #error IOH_I2S_CH0_CONFIG Error : \ Sampling frequency 8000Hz can not generate. #endif #endif #ifdef I2S_CH0_FS_11025 #if (I2S_CH0_64FS != I2S_CH0_FS_11025) && \ (I2S_CH0_128FS != I2S_CH0_FS_11025) && \ (I2S_CH0_192FS != I2S_CH0_FS_11025) && \ (I2S_CH0_256FS != I2S_CH0_FS_11025) && \ (I2S_CH0_384FS != I2S_CH0_FS_11025) && \ (I2S_CH0_512FS != I2S_CH0_FS_11025) && \ (I2S_CH0_768FS != I2S_CH0_FS_11025) && \ (I2S_CH0_1024FS != I2S_CH0_FS_11025) #error IOH_I2S_CH0_CONFIG Error : \ Sampling frequency 11025Hz can not generate. #endif #endif #ifdef I2S_CH0_FS_16000 #if (I2S_CH0_64FS != I2S_CH0_FS_16000) && \ (I2S_CH0_128FS != I2S_CH0_FS_16000) && \ (I2S_CH0_192FS != I2S_CH0_FS_16000) && \ (I2S_CH0_256FS != I2S_CH0_FS_16000) && \ (I2S_CH0_384FS != I2S_CH0_FS_16000) && \ (I2S_CH0_512FS != I2S_CH0_FS_16000) && \ (I2S_CH0_768FS != I2S_CH0_FS_16000) && \ (I2S_CH0_1024FS != I2S_CH0_FS_16000) #error IOH_I2S_CH0_CONFIG Error : \ Sampling frequency 16000Hz can not generate. #endif #endif #ifdef I2S_CH0_FS_22050 #if (I2S_CH0_64FS != I2S_CH0_FS_22050) && \ (I2S_CH0_128FS != I2S_CH0_FS_22050) && \ (I2S_CH0_192FS != I2S_CH0_FS_22050) && \ (I2S_CH0_256FS != I2S_CH0_FS_22050) && \ (I2S_CH0_384FS != I2S_CH0_FS_22050) && \ (I2S_CH0_512FS != I2S_CH0_FS_22050) && \ (I2S_CH0_768FS != I2S_CH0_FS_22050) && \ (I2S_CH0_1024FS != I2S_CH0_FS_22050) #error IOH_I2S_CH0_CONFIG Error : \ Sampling frequency 22050Hz can not generate. #endif #endif #ifdef I2S_CH0_FS_32000 #if (I2S_CH0_64FS != I2S_CH0_FS_32000) && \ (I2S_CH0_128FS != I2S_CH0_FS_32000) && \ (I2S_CH0_192FS != I2S_CH0_FS_32000) && \ (I2S_CH0_256FS != I2S_CH0_FS_32000) && \ (I2S_CH0_384FS != I2S_CH0_FS_32000) && \ (I2S_CH0_512FS != I2S_CH0_FS_32000) && \ (I2S_CH0_768FS != I2S_CH0_FS_32000) && \ (I2S_CH0_1024FS != I2S_CH0_FS_32000) #error IOH_I2S_CH0_CONFIG Error : \ Sampling frequency 32000Hz can not generate. #endif #endif #ifdef I2S_CH0_FS_44100 #if (I2S_CH0_64FS != I2S_CH0_FS_44100) && \ (I2S_CH0_128FS != I2S_CH0_FS_44100) && \ (I2S_CH0_192FS != I2S_CH0_FS_44100) && \ (I2S_CH0_256FS != I2S_CH0_FS_44100) && \ (I2S_CH0_384FS != I2S_CH0_FS_44100) && \ (I2S_CH0_512FS != I2S_CH0_FS_44100) && \ (I2S_CH0_768FS != I2S_CH0_FS_44100) && \ (I2S_CH0_1024FS != I2S_CH0_FS_44100) #error IOH_I2S_CH0_CONFIG Error : \ Sampling frequency 44100Hz can not generate. #endif #endif #ifdef I2S_CH0_FS_48000 #if (I2S_CH0_64FS != I2S_CH0_FS_48000) && \ (I2S_CH0_128FS != I2S_CH0_FS_48000) && \ (I2S_CH0_192FS != I2S_CH0_FS_48000) && \ (I2S_CH0_256FS != I2S_CH0_FS_48000) && \ (I2S_CH0_384FS != I2S_CH0_FS_48000) && \ (I2S_CH0_512FS != I2S_CH0_FS_48000) && \ (I2S_CH0_768FS != I2S_CH0_FS_48000) && \ (I2S_CH0_1024FS != I2S_CH0_FS_48000) #error IOH_I2S_CH0_CONFIG Error : \ Sampling frequency 48000Hz can not generate. #endif #endif #endif /* end of [#if (I2S_CH0_MSSEL == ioh_mssel_master)] */ /* ===== CH1 Parameter Error Check ==== */ #define USE_RATE_MAX_CH1 (0) #ifdef I2S_CH1_FS_8000 #define USE_RATE_CH1_8000 SNDRV_PCM_RATE_8000 #define USE_RATE_MIN_CH1 (8000) #if (USE_RATE_MAX_CH1 < 8000) #undef USE_RATE_MAX_CH1 #define USE_RATE_MAX_CH1 (8000) #endif #else #define USE_RATE_CH1_8000 0 #endif #ifdef I2S_CH1_FS_11025 #define USE_RATE_CH1_11025 SNDRV_PCM_RATE_11025 #ifndef USE_RATE_MIN_CH1 #define USE_RATE_MIN_CH1 (11025) #endif #if (USE_RATE_MAX_CH1 < 11025) #undef USE_RATE_MAX_CH1 #define USE_RATE_MAX_CH1 (11025) #endif #else #define USE_RATE_CH1_11025 0 #endif #ifdef I2S_CH1_FS_16000 #define USE_RATE_CH1_16000 SNDRV_PCM_RATE_16000 #ifndef USE_RATE_MIN_CH1 #define USE_RATE_MIN_CH1 (16000) #endif #if (USE_RATE_MAX_CH1 < 16000) #undef USE_RATE_MAX_CH1 #define USE_RATE_MAX_CH1 (16000) #endif #else #define USE_RATE_CH1_16000 0 #endif #ifdef I2S_CH1_FS_22050 #define USE_RATE_CH1_22050 SNDRV_PCM_RATE_22050 #ifndef USE_RATE_MIN_CH1 #define USE_RATE_MIN_CH1 (22050) #endif #if (USE_RATE_MAX_CH1 < 22050) #undef USE_RATE_MAX_CH1 #define USE_RATE_MAX_CH1 (22050) #endif #else #define USE_RATE_CH1_22050 0 #endif #ifdef I2S_CH1_FS_32000 #define USE_RATE_CH1_32000 SNDRV_PCM_RATE_32000 #ifndef USE_RATE_MIN_CH1 #define USE_RATE_MIN_CH1 (32000) #endif #if (USE_RATE_MAX_CH1 < 32000) #undef USE_RATE_MAX_CH1 #define USE_RATE_MAX_CH1 (32000) #endif #else #define USE_RATE_CH1_32000 0 #endif #ifdef I2S_CH1_FS_44100 #define USE_RATE_CH1_44100 SNDRV_PCM_RATE_44100 #ifndef USE_RATE_MIN_CH1 #define USE_RATE_MIN_CH1 (44100) #endif #if (USE_RATE_MAX_CH1 < 44100) #undef USE_RATE_MAX_CH1 #define USE_RATE_MAX_CH1 (44100) #endif #else #define USE_RATE_CH1_44100 0 #endif #ifdef I2S_CH1_FS_48000 #define USE_RATE_CH1_48000 SNDRV_PCM_RATE_48000 #ifndef USE_RATE_MIN_CH1 #define USE_RATE_MIN_CH1 (48000) #endif #if (USE_RATE_MAX_CH1 < 48000) #undef USE_RATE_MAX_CH1 #define USE_RATE_MAX_CH1 (48000) #endif #else #define USE_RATE_CH1_48000 0 #endif #define USE_RATE_CH1 (USE_RATE_CH1_8000|USE_RATE_CH1_11025 | \ USE_RATE_CH1_16000|USE_RATE_CH1_22050 | \ USE_RATE_CH1_32000|USE_RATE_CH1_44100 | \ USE_RATE_CH1_48000) #define I2S_CH1_64FS (I2S_CH1_MCLK/64) #define I2S_CH1_128FS (I2S_CH1_MCLK/128) #define I2S_CH1_192FS (I2S_CH1_MCLK/192) #define I2S_CH1_256FS (I2S_CH1_MCLK/256) #define I2S_CH1_384FS (I2S_CH1_MCLK/384) #define I2S_CH1_512FS (I2S_CH1_MCLK/512) #define I2S_CH1_768FS (I2S_CH1_MCLK/768) #define I2S_CH1_1024FS (I2S_CH1_MCLK/1024) #if (I2S_CH1_MSSEL == ioh_mssel_master) #ifdef I2S_CH1_FS_8000 #if (I2S_CH1_64FS != I2S_CH1_FS_8000) && \ (I2S_CH1_128FS != I2S_CH1_FS_8000) && \ (I2S_CH1_192FS != I2S_CH1_FS_8000) && \ (I2S_CH1_256FS != I2S_CH1_FS_8000) && \ (I2S_CH1_384FS != I2S_CH1_FS_8000) && \ (I2S_CH1_512FS != I2S_CH1_FS_8000) && \ (I2S_CH1_768FS != I2S_CH1_FS_8000) && \ (I2S_CH1_1024FS != I2S_CH1_FS_8000) #error IOH_I2S_CH1_CONFIG Error : \ Sampling frequency 8000Hz can not generate. #endif #endif #ifdef I2S_CH1_FS_11025 #if (I2S_CH1_64FS != I2S_CH1_FS_11025) && \ (I2S_CH1_128FS != I2S_CH1_FS_11025) && \ (I2S_CH1_192FS != I2S_CH1_FS_11025) && \ (I2S_CH1_256FS != I2S_CH1_FS_11025) && \ (I2S_CH1_384FS != I2S_CH1_FS_11025) && \ (I2S_CH1_512FS != I2S_CH1_FS_11025) && \ (I2S_CH1_768FS != I2S_CH1_FS_11025) && \ (I2S_CH1_1024FS != I2S_CH1_FS_11025) #error IOH_I2S_CH1_CONFIG Error : \ Sampling frequency 11025Hz can not generate. #endif #endif #ifdef I2S_CH1_FS_16000 #if (I2S_CH1_64FS != I2S_CH1_FS_16000) && \ (I2S_CH1_128FS != I2S_CH1_FS_16000) && \ (I2S_CH1_192FS != I2S_CH1_FS_16000) && \ (I2S_CH1_256FS != I2S_CH1_FS_16000) && \ (I2S_CH1_384FS != I2S_CH1_FS_16000) && \ (I2S_CH1_512FS != I2S_CH1_FS_16000) && \ (I2S_CH1_768FS != I2S_CH1_FS_16000) && \ (I2S_CH1_1024FS != I2S_CH1_FS_16000) #error IOH_I2S_CH1_CONFIG Error : \ Sampling frequency 16000Hz can not generate. #endif #endif #ifdef I2S_CH1_FS_22050 #if (I2S_CH1_64FS != I2S_CH1_FS_22050) && \ (I2S_CH1_128FS != I2S_CH1_FS_22050) && \ (I2S_CH1_192FS != I2S_CH1_FS_22050) && \ (I2S_CH1_256FS != I2S_CH1_FS_22050) && \ (I2S_CH1_384FS != I2S_CH1_FS_22050) && \ (I2S_CH1_512FS != I2S_CH1_FS_22050) && \ (I2S_CH1_768FS != I2S_CH1_FS_22050) && \ (I2S_CH1_1024FS != I2S_CH1_FS_22050) #error IOH_I2S_CH1_CONFIG Error : \ Sampling frequency 22050Hz can not generate. #endif #endif #ifdef I2S_CH1_FS_32000 #if (I2S_CH1_64FS != I2S_CH1_FS_32000) && \ (I2S_CH1_128FS != I2S_CH1_FS_32000) && \ (I2S_CH1_192FS != I2S_CH1_FS_32000) && \ (I2S_CH1_256FS != I2S_CH1_FS_32000) && \ (I2S_CH1_384FS != I2S_CH1_FS_32000) && \ (I2S_CH1_512FS != I2S_CH1_FS_32000) && \ (I2S_CH1_768FS != I2S_CH1_FS_32000) && \ (I2S_CH1_1024FS != I2S_CH1_FS_32000) #error IOH_I2S_CH1_CONFIG Error : \ Sampling frequency 32000Hz can not generate. #endif #endif #ifdef I2S_CH1_FS_44100 #if (I2S_CH1_64FS != I2S_CH1_FS_44100) && \ (I2S_CH1_128FS != I2S_CH1_FS_44100) && \ (I2S_CH1_192FS != I2S_CH1_FS_44100) && \ (I2S_CH1_256FS != I2S_CH1_FS_44100) && \ (I2S_CH1_384FS != I2S_CH1_FS_44100) && \ (I2S_CH1_512FS != I2S_CH1_FS_44100) && \ (I2S_CH1_768FS != I2S_CH1_FS_44100) && \ (I2S_CH1_1024FS != I2S_CH1_FS_44100) #error IOH_I2S_CH1_CONFIG Error : \ Sampling frequency 44100Hz can not generate. #endif #endif #ifdef I2S_CH1_FS_48000 #if (I2S_CH1_64FS != I2S_CH1_FS_48000) && \ (I2S_CH1_128FS != I2S_CH1_FS_48000) && \ (I2S_CH1_192FS != I2S_CH1_FS_48000) && \ (I2S_CH1_256FS != I2S_CH1_FS_48000) && \ (I2S_CH1_384FS != I2S_CH1_FS_48000) && \ (I2S_CH1_512FS != I2S_CH1_FS_48000) && \ (I2S_CH1_768FS != I2S_CH1_FS_48000) && \ (I2S_CH1_1024FS != I2S_CH1_FS_48000) #error IOH_I2S_CH1_CONFIG Error : \ Sampling frequency 48000Hz can not generate. #endif #endif #endif /* end of [#if (I2S_CH1_MSSEL == ioh_mssel_master)] */ /* ===== CH2 Parameter Error Check ==== */ #define USE_RATE_MAX_CH2 (0) #ifdef I2S_CH2_FS_8000 #define USE_RATE_CH2_8000 SNDRV_PCM_RATE_8000 #define USE_RATE_MIN_CH2 (8000) #if (USE_RATE_MAX_CH2 < 8000) #undef USE_RATE_MAX_CH2 #define USE_RATE_MAX_CH2 (8000) #endif #else #define USE_RATE_CH2_8000 0 #endif #ifdef I2S_CH2_FS_11025 #define USE_RATE_CH2_11025 SNDRV_PCM_RATE_11025 #ifndef USE_RATE_MIN_CH2 #define USE_RATE_MIN_CH2 (11025) #endif #if (USE_RATE_MAX_CH2 < 11025) #undef USE_RATE_MAX_CH2 #define USE_RATE_MAX_CH2 (11025) #endif #else #define USE_RATE_CH2_11025 0 #endif #ifdef I2S_CH2_FS_16000 #define USE_RATE_CH2_16000 SNDRV_PCM_RATE_16000 #ifndef USE_RATE_MIN_CH2 #define USE_RATE_MIN_CH2 (16000) #endif #if (USE_RATE_MAX_CH2 < 16000) #undef USE_RATE_MAX_CH2 #define USE_RATE_MAX_CH2 (16000) #endif #else #define USE_RATE_CH2_16000 0 #endif #ifdef I2S_CH2_FS_22050 #define USE_RATE_CH2_22050 SNDRV_PCM_RATE_22050 #ifndef USE_RATE_MIN_CH2 #define USE_RATE_MIN_CH2 (22050) #endif #if (USE_RATE_MAX_CH2 < 22050) #undef USE_RATE_MAX_CH2 #define USE_RATE_MAX_CH2 (22050) #endif #else #define USE_RATE_CH2_22050 0 #endif #ifdef I2S_CH2_FS_32000 #define USE_RATE_CH2_32000 SNDRV_PCM_RATE_32000 #ifndef USE_RATE_MIN_CH2 #define USE_RATE_MIN_CH2 (32000) #endif #if (USE_RATE_MAX_CH2 < 32000) #undef USE_RATE_MAX_CH2 #define USE_RATE_MAX_CH2 (32000) #endif #else #define USE_RATE_CH2_32000 0 #endif #ifdef I2S_CH2_FS_44100 #define USE_RATE_CH2_44100 SNDRV_PCM_RATE_44100 #ifndef USE_RATE_MIN_CH2 #define USE_RATE_MIN_CH2 (44100) #endif #if (USE_RATE_MAX_CH2 < 44100) #undef USE_RATE_MAX_CH2 #define USE_RATE_MAX_CH2 (44100) #endif #else #define USE_RATE_CH2_44100 0 #endif #ifdef I2S_CH2_FS_48000 #define USE_RATE_CH2_48000 SNDRV_PCM_RATE_48000 #ifndef USE_RATE_MIN_CH2 #define USE_RATE_MIN_CH2 (48000) #endif #if (USE_RATE_MAX_CH2 < 48000) #undef USE_RATE_MAX_CH2 #define USE_RATE_MAX_CH2 (48000) #endif #else #define USE_RATE_CH2_48000 0 #endif #define USE_RATE_CH2 (USE_RATE_CH2_8000|USE_RATE_CH2_11025 | \ USE_RATE_CH2_16000|USE_RATE_CH2_22050 | \ USE_RATE_CH2_32000|USE_RATE_CH2_44100 | \ USE_RATE_CH2_48000) #define I2S_CH2_64FS (I2S_CH2_MCLK/64) #define I2S_CH2_128FS (I2S_CH2_MCLK/128) #define I2S_CH2_192FS (I2S_CH2_MCLK/192) #define I2S_CH2_256FS (I2S_CH2_MCLK/256) #define I2S_CH2_384FS (I2S_CH2_MCLK/384) #define I2S_CH2_512FS (I2S_CH2_MCLK/512) #define I2S_CH2_768FS (I2S_CH2_MCLK/768) #define I2S_CH2_1024FS (I2S_CH2_MCLK/1024) #if (I2S_CH2_MSSEL == ioh_mssel_master) #ifdef I2S_CH2_FS_8000 #if (I2S_CH2_64FS != I2S_CH2_FS_8000) && \ (I2S_CH2_128FS != I2S_CH2_FS_8000) && \ (I2S_CH2_192FS != I2S_CH2_FS_8000) && \ (I2S_CH2_256FS != I2S_CH2_FS_8000) && \ (I2S_CH2_384FS != I2S_CH2_FS_8000) && \ (I2S_CH2_512FS != I2S_CH2_FS_8000) && \ (I2S_CH2_768FS != I2S_CH2_FS_8000) && \ (I2S_CH2_1024FS != I2S_CH2_FS_8000) #error IOH_I2S_CH2_CONFIG Error : \ Sampling frequency 8000Hz can not generate. #endif #endif #ifdef I2S_CH2_FS_11025 #if (I2S_CH2_64FS != I2S_CH2_FS_11025) && \ (I2S_CH2_128FS != I2S_CH2_FS_11025) && \ (I2S_CH2_192FS != I2S_CH2_FS_11025) && \ (I2S_CH2_256FS != I2S_CH2_FS_11025) && \ (I2S_CH2_384FS != I2S_CH2_FS_11025) && \ (I2S_CH2_512FS != I2S_CH2_FS_11025) && \ (I2S_CH2_768FS != I2S_CH2_FS_11025) && \ (I2S_CH2_1024FS != I2S_CH2_FS_11025) #error IOH_I2S_CH2_CONFIG Error : \ Sampling frequency 11025Hz can not generate. #endif #endif #ifdef I2S_CH2_FS_16000 #if (I2S_CH2_64FS != I2S_CH2_FS_16000) && \ (I2S_CH2_128FS != I2S_CH2_FS_16000) && \ (I2S_CH2_192FS != I2S_CH2_FS_16000) && \ (I2S_CH2_256FS != I2S_CH2_FS_16000) && \ (I2S_CH2_384FS != I2S_CH2_FS_16000) && \ (I2S_CH2_512FS != I2S_CH2_FS_16000) && \ (I2S_CH2_768FS != I2S_CH2_FS_16000) && \ (I2S_CH2_1024FS != I2S_CH2_FS_16000) #error IOH_I2S_CH2_CONFIG Error : \ Sampling frequency 16000Hz can not generate. #endif #endif #ifdef I2S_CH2_FS_22050 #if (I2S_CH2_64FS != I2S_CH2_FS_22050) && \ (I2S_CH2_128FS != I2S_CH2_FS_22050) && \ (I2S_CH2_192FS != I2S_CH2_FS_22050) && \ (I2S_CH2_256FS != I2S_CH2_FS_22050) && \ (I2S_CH2_384FS != I2S_CH2_FS_22050) && \ (I2S_CH2_512FS != I2S_CH2_FS_22050) && \ (I2S_CH2_768FS != I2S_CH2_FS_22050) && \ (I2S_CH2_1024FS != I2S_CH2_FS_22050) #error IOH_I2S_CH2_CONFIG Error : \ Sampling frequency 22050Hz can not generate. #endif #endif #ifdef I2S_CH2_FS_32000 #if (I2S_CH2_64FS != I2S_CH2_FS_32000) && \ (I2S_CH2_128FS != I2S_CH2_FS_32000) && \ (I2S_CH2_192FS != I2S_CH2_FS_32000) && \ (I2S_CH2_256FS != I2S_CH2_FS_32000) && \ (I2S_CH2_384FS != I2S_CH2_FS_32000) && \ (I2S_CH2_512FS != I2S_CH2_FS_32000) && \ (I2S_CH2_768FS != I2S_CH2_FS_32000) && \ (I2S_CH2_1024FS != I2S_CH2_FS_32000) #error IOH_I2S_CH2_CONFIG Error : \ Sampling frequency 32000Hz can not generate. #endif #endif #ifdef I2S_CH2_FS_44100 #if (I2S_CH2_64FS != I2S_CH2_FS_44100) && \ (I2S_CH2_128FS != I2S_CH2_FS_44100) && \ (I2S_CH2_192FS != I2S_CH2_FS_44100) && \ (I2S_CH2_256FS != I2S_CH2_FS_44100) && \ (I2S_CH2_384FS != I2S_CH2_FS_44100) && \ (I2S_CH2_512FS != I2S_CH2_FS_44100) && \ (I2S_CH2_768FS != I2S_CH2_FS_44100) && \ (I2S_CH2_1024FS != I2S_CH2_FS_44100) #error IOH_I2S_CH2_CONFIG Error : \ Sampling frequency 44100Hz can not generate. #endif #endif #ifdef I2S_CH2_FS_48000 #if (I2S_CH2_64FS != I2S_CH2_FS_48000) && \ (I2S_CH2_128FS != I2S_CH2_FS_48000) && \ (I2S_CH2_192FS != I2S_CH2_FS_48000) && \ (I2S_CH2_256FS != I2S_CH2_FS_48000) && \ (I2S_CH2_384FS != I2S_CH2_FS_48000) && \ (I2S_CH2_512FS != I2S_CH2_FS_48000) && \ (I2S_CH2_768FS != I2S_CH2_FS_48000) && \ (I2S_CH2_1024FS != I2S_CH2_FS_48000) #error IOH_I2S_CH2_CONFIG Error : \ Sampling frequency 48000Hz can not generate. #endif #endif #endif /* end of [#if (I2S_CH2_MSSEL == ioh_mssel_master)] */ /* ===== CH3 Parameter Error Check ==== */ #define USE_RATE_MAX_CH3 (0) #ifdef I2S_CH3_FS_8000 #define USE_RATE_CH3_8000 SNDRV_PCM_RATE_8000 #define USE_RATE_MIN_CH3 (8000) #if (USE_RATE_MAX_CH3 < 8000) #undef USE_RATE_MAX_CH3 #define USE_RATE_MAX_CH3 (8000) #endif #else #define USE_RATE_CH3_8000 0 #endif #ifdef I2S_CH3_FS_11025 #define USE_RATE_CH3_11025 SNDRV_PCM_RATE_11025 #ifndef USE_RATE_MIN_CH3 #define USE_RATE_MIN_CH3 (11025) #endif #if (USE_RATE_MAX_CH3 < 11025) #undef USE_RATE_MAX_CH3 #define USE_RATE_MAX_CH3 (11025) #endif #else #define USE_RATE_CH3_11025 0 #endif #ifdef I2S_CH3_FS_16000 #define USE_RATE_CH3_16000 SNDRV_PCM_RATE_16000 #ifndef USE_RATE_MIN_CH3 #define USE_RATE_MIN_CH3 (16000) #endif #if (USE_RATE_MAX_CH3 < 16000) #undef USE_RATE_MAX_CH3 #define USE_RATE_MAX_CH3 (16000) #endif #else #define USE_RATE_CH3_16000 0 #endif #ifdef I2S_CH3_FS_22050 #define USE_RATE_CH3_22050 SNDRV_PCM_RATE_22050 #ifndef USE_RATE_MIN_CH3 #define USE_RATE_MIN_CH3 (22050) #endif #if (USE_RATE_MAX_CH3 < 22050) #undef USE_RATE_MAX_CH3 #define USE_RATE_MAX_CH3 (22050) #endif #else #define USE_RATE_CH3_22050 0 #endif #ifdef I2S_CH3_FS_32000 #define USE_RATE_CH3_32000 SNDRV_PCM_RATE_32000 #ifndef USE_RATE_MIN_CH3 #define USE_RATE_MIN_CH3 (32000) #endif #if (USE_RATE_MAX_CH3 < 32000) #undef USE_RATE_MAX_CH3 #define USE_RATE_MAX_CH3 (32000) #endif #else #define USE_RATE_CH3_32000 0 #endif #ifdef I2S_CH3_FS_44100 #define USE_RATE_CH3_44100 SNDRV_PCM_RATE_44100 #ifndef USE_RATE_MIN_CH3 #define USE_RATE_MIN_CH3 (44100) #endif #if (USE_RATE_MAX_CH3 < 44100) #undef USE_RATE_MAX_CH3 #define USE_RATE_MAX_CH3 (44100) #endif #else #define USE_RATE_CH3_44100 0 #endif #ifdef I2S_CH3_FS_48000 #define USE_RATE_CH3_48000 SNDRV_PCM_RATE_48000 #ifndef USE_RATE_MIN_CH3 #define USE_RATE_MIN_CH3 (48000) #endif #if (USE_RATE_MAX_CH3 < 48000) #undef USE_RATE_MAX_CH3 #define USE_RATE_MAX_CH3 (48000) #endif #else #define USE_RATE_CH3_48000 0 #endif #define USE_RATE_CH3 (USE_RATE_CH3_8000|USE_RATE_CH3_11025 | \ USE_RATE_CH3_16000|USE_RATE_CH3_22050 | \ USE_RATE_CH3_32000|USE_RATE_CH3_44100 | \ USE_RATE_CH3_48000) #define I2S_CH3_64FS (I2S_CH3_MCLK/64) #define I2S_CH3_128FS (I2S_CH3_MCLK/128) #define I2S_CH3_192FS (I2S_CH3_MCLK/192) #define I2S_CH3_256FS (I2S_CH3_MCLK/256) #define I2S_CH3_384FS (I2S_CH3_MCLK/384) #define I2S_CH3_512FS (I2S_CH3_MCLK/512) #define I2S_CH3_768FS (I2S_CH3_MCLK/768) #define I2S_CH3_1024FS (I2S_CH3_MCLK/1024) #if (I2S_CH3_MSSEL == ioh_mssel_master) #ifdef I2S_CH3_FS_8000 #if (I2S_CH3_64FS != I2S_CH3_FS_8000) && \ (I2S_CH3_128FS != I2S_CH3_FS_8000) && \ (I2S_CH3_192FS != I2S_CH3_FS_8000) && \ (I2S_CH3_256FS != I2S_CH3_FS_8000) && \ (I2S_CH3_384FS != I2S_CH3_FS_8000) && \ (I2S_CH3_512FS != I2S_CH3_FS_8000) && \ (I2S_CH3_768FS != I2S_CH3_FS_8000) && \ (I2S_CH3_1024FS != I2S_CH3_FS_8000) #error IOH_I2S_CH3_CONFIG Error : \ Sampling frequency 8000Hz can not generate. #endif #endif #ifdef I2S_CH3_FS_11025 #if (I2S_CH3_64FS != I2S_CH3_FS_11025) && \ (I2S_CH3_128FS != I2S_CH3_FS_11025) && \ (I2S_CH3_192FS != I2S_CH3_FS_11025) && \ (I2S_CH3_256FS != I2S_CH3_FS_11025) && \ (I2S_CH3_384FS != I2S_CH3_FS_11025) && \ (I2S_CH3_512FS != I2S_CH3_FS_11025) && \ (I2S_CH3_768FS != I2S_CH3_FS_11025) && \ (I2S_CH3_1024FS != I2S_CH3_FS_11025) #error IOH_I2S_CH3_CONFIG Error : \ Sampling frequency 11025Hz can not generate. #endif #endif #ifdef I2S_CH3_FS_16000 #if (I2S_CH3_64FS != I2S_CH3_FS_16000) && \ (I2S_CH3_128FS != I2S_CH3_FS_16000) && \ (I2S_CH3_192FS != I2S_CH3_FS_16000) && \ (I2S_CH3_256FS != I2S_CH3_FS_16000) && \ (I2S_CH3_384FS != I2S_CH3_FS_16000) && \ (I2S_CH3_512FS != I2S_CH3_FS_16000) && \ (I2S_CH3_768FS != I2S_CH3_FS_16000) && \ (I2S_CH3_1024FS != I2S_CH3_FS_16000) #error IOH_I2S_CH3_CONFIG Error : \ Sampling frequency 16000Hz can not generate. #endif #endif #ifdef I2S_CH3_FS_22050 #if (I2S_CH3_64FS != I2S_CH3_FS_22050) && \ (I2S_CH3_128FS != I2S_CH3_FS_22050) && \ (I2S_CH3_192FS != I2S_CH3_FS_22050) && \ (I2S_CH3_256FS != I2S_CH3_FS_22050) && \ (I2S_CH3_384FS != I2S_CH3_FS_22050) && \ (I2S_CH3_512FS != I2S_CH3_FS_22050) && \ (I2S_CH3_768FS != I2S_CH3_FS_22050) && \ (I2S_CH3_1024FS != I2S_CH3_FS_22050) #error IOH_I2S_CH3_CONFIG Error : \ Sampling frequency 22050Hz can not generate. #endif #endif #ifdef I2S_CH3_FS_32000 #if (I2S_CH3_64FS != I2S_CH3_FS_32000) && \ (I2S_CH3_128FS != I2S_CH3_FS_32000) && \ (I2S_CH3_192FS != I2S_CH3_FS_32000) && \ (I2S_CH3_256FS != I2S_CH3_FS_32000) && \ (I2S_CH3_384FS != I2S_CH3_FS_32000) && \ (I2S_CH3_512FS != I2S_CH3_FS_32000) && \ (I2S_CH3_768FS != I2S_CH3_FS_32000) && \ (I2S_CH3_1024FS != I2S_CH3_FS_32000) #error IOH_I2S_CH3_CONFIG Error : \ Sampling frequency 32000Hz can not generate. #endif #endif #ifdef I2S_CH3_FS_44100 #if (I2S_CH3_64FS != I2S_CH3_FS_44100) && \ (I2S_CH3_128FS != I2S_CH3_FS_44100) && \ (I2S_CH3_192FS != I2S_CH3_FS_44100) && \ (I2S_CH3_256FS != I2S_CH3_FS_44100) && \ (I2S_CH3_384FS != I2S_CH3_FS_44100) && \ (I2S_CH3_512FS != I2S_CH3_FS_44100) && \ (I2S_CH3_768FS != I2S_CH3_FS_44100) && \ (I2S_CH3_1024FS != I2S_CH3_FS_44100) #error IOH_I2S_CH3_CONFIG Error : \ Sampling frequency 44100Hz can not generate. #endif #endif #ifdef I2S_CH3_FS_48000 #if (I2S_CH3_64FS != I2S_CH3_FS_48000) && \ (I2S_CH3_128FS != I2S_CH3_FS_48000) && \ (I2S_CH3_192FS != I2S_CH3_FS_48000) && \ (I2S_CH3_256FS != I2S_CH3_FS_48000) && \ (I2S_CH3_384FS != I2S_CH3_FS_48000) && \ (I2S_CH3_512FS != I2S_CH3_FS_48000) && \ (I2S_CH3_768FS != I2S_CH3_FS_48000) && \ (I2S_CH3_1024FS != I2S_CH3_FS_48000) #error IOH_I2S_CH3_CONFIG Error : \ Sampling frequency 48000Hz can not generate. #endif #endif #endif /* end of [#if (I2S_CH3_MSSEL == ioh_mssel_master)] */ /* ===== CH4 Parameter Error Check ==== */ #define USE_RATE_MAX_CH4 (0) #ifdef I2S_CH4_FS_8000 #define USE_RATE_CH4_8000 SNDRV_PCM_RATE_8000 #define USE_RATE_MIN_CH4 (8000) #if (USE_RATE_MAX_CH4 < 8000) #undef USE_RATE_MAX_CH4 #define USE_RATE_MAX_CH4 (8000) #endif #else #define USE_RATE_CH4_8000 0 #endif #ifdef I2S_CH4_FS_11025 #define USE_RATE_CH4_11025 SNDRV_PCM_RATE_11025 #ifndef USE_RATE_MIN_CH4 #define USE_RATE_MIN_CH4 (11025) #endif #if (USE_RATE_MAX_CH4 < 11025) #undef USE_RATE_MAX_CH4 #define USE_RATE_MAX_CH4 (11025) #endif #else #define USE_RATE_CH4_11025 0 #endif #ifdef I2S_CH4_FS_16000 #define USE_RATE_CH4_16000 SNDRV_PCM_RATE_16000 #ifndef USE_RATE_MIN_CH4 #define USE_RATE_MIN_CH4 (16000) #endif #if (USE_RATE_MAX_CH4 < 16000) #undef USE_RATE_MAX_CH4 #define USE_RATE_MAX_CH4 (16000) #endif #else #define USE_RATE_CH4_16000 0 #endif #ifdef I2S_CH4_FS_22050 #define USE_RATE_CH4_22050 SNDRV_PCM_RATE_22050 #ifndef USE_RATE_MIN_CH4 #define USE_RATE_MIN_CH4 (22050) #endif #if (USE_RATE_MAX_CH4 < 22050) #undef USE_RATE_MAX_CH4 #define USE_RATE_MAX_CH4 (22050) #endif #else #define USE_RATE_CH4_22050 0 #endif #ifdef I2S_CH4_FS_32000 #define USE_RATE_CH4_32000 SNDRV_PCM_RATE_32000 #ifndef USE_RATE_MIN_CH4 #define USE_RATE_MIN_CH4 (32000) #endif #if (USE_RATE_MAX_CH4 < 32000) #undef USE_RATE_MAX_CH4 #define USE_RATE_MAX_CH4 (32000) #endif #else #define USE_RATE_CH4_32000 0 #endif #ifdef I2S_CH4_FS_44100 #define USE_RATE_CH4_44100 SNDRV_PCM_RATE_44100 #ifndef USE_RATE_MIN_CH4 #define USE_RATE_MIN_CH4 (44100) #endif #if (USE_RATE_MAX_CH4 < 44100) #undef USE_RATE_MAX_CH4 #define USE_RATE_MAX_CH4 (44100) #endif #else #define USE_RATE_CH4_44100 0 #endif #ifdef I2S_CH4_FS_48000 #define USE_RATE_CH4_48000 SNDRV_PCM_RATE_48000 #ifndef USE_RATE_MIN_CH4 #define USE_RATE_MIN_CH4 (48000) #endif #if (USE_RATE_MAX_CH4 < 48000) #undef USE_RATE_MAX_CH4 #define USE_RATE_MAX_CH4 (48000) #endif #else #define USE_RATE_CH4_48000 0 #endif #define USE_RATE_CH4 (USE_RATE_CH4_8000|USE_RATE_CH4_11025 | \ USE_RATE_CH4_16000|USE_RATE_CH4_22050 | \ USE_RATE_CH4_32000|USE_RATE_CH4_44100 | \ USE_RATE_CH4_48000) #define I2S_CH4_64FS (I2S_CH4_MCLK/64) #define I2S_CH4_128FS (I2S_CH4_MCLK/128) #define I2S_CH4_192FS (I2S_CH4_MCLK/192) #define I2S_CH4_256FS (I2S_CH4_MCLK/256) #define I2S_CH4_384FS (I2S_CH4_MCLK/384) #define I2S_CH4_512FS (I2S_CH4_MCLK/512) #define I2S_CH4_768FS (I2S_CH4_MCLK/768) #define I2S_CH4_1024FS (I2S_CH4_MCLK/1024) #if (I2S_CH4_MSSEL == ioh_mssel_master) #ifdef I2S_CH4_FS_8000 #if (I2S_CH4_64FS != I2S_CH4_FS_8000) && \ (I2S_CH4_128FS != I2S_CH4_FS_8000) && \ (I2S_CH4_192FS != I2S_CH4_FS_8000) && \ (I2S_CH4_256FS != I2S_CH4_FS_8000) && \ (I2S_CH4_384FS != I2S_CH4_FS_8000) && \ (I2S_CH4_512FS != I2S_CH4_FS_8000) && \ (I2S_CH4_768FS != I2S_CH4_FS_8000) && \ (I2S_CH4_1024FS != I2S_CH4_FS_8000) #error IOH_I2S_CH4_CONFIG Error : \ Sampling frequency 8000Hz can not generate. #endif #endif #ifdef I2S_CH4_FS_11025 #if (I2S_CH4_64FS != I2S_CH4_FS_11025) && \ (I2S_CH4_128FS != I2S_CH4_FS_11025) && \ (I2S_CH4_192FS != I2S_CH4_FS_11025) && \ (I2S_CH4_256FS != I2S_CH4_FS_11025) && \ (I2S_CH4_384FS != I2S_CH4_FS_11025) && \ (I2S_CH4_512FS != I2S_CH4_FS_11025) && \ (I2S_CH4_768FS != I2S_CH4_FS_11025) && \ (I2S_CH4_1024FS != I2S_CH4_FS_11025) #error IOH_I2S_CH4_CONFIG Error : \ Sampling frequency 11025Hz can not generate. #endif #endif #ifdef I2S_CH4_FS_16000 #if (I2S_CH4_64FS != I2S_CH4_FS_16000) && \ (I2S_CH4_128FS != I2S_CH4_FS_16000) && \ (I2S_CH4_192FS != I2S_CH4_FS_16000) && \ (I2S_CH4_256FS != I2S_CH4_FS_16000) && \ (I2S_CH4_384FS != I2S_CH4_FS_16000) && \ (I2S_CH4_512FS != I2S_CH4_FS_16000) && \ (I2S_CH4_768FS != I2S_CH4_FS_16000) && \ (I2S_CH4_1024FS != I2S_CH4_FS_16000) #error IOH_I2S_CH4_CONFIG Error : \ Sampling frequency 16000Hz can not generate. #endif #endif #ifdef I2S_CH4_FS_22050 #if (I2S_CH4_64FS != I2S_CH4_FS_22050) && \ (I2S_CH4_128FS != I2S_CH4_FS_22050) && \ (I2S_CH4_192FS != I2S_CH4_FS_22050) && \ (I2S_CH4_256FS != I2S_CH4_FS_22050) && \ (I2S_CH4_384FS != I2S_CH4_FS_22050) && \ (I2S_CH4_512FS != I2S_CH4_FS_22050) && \ (I2S_CH4_768FS != I2S_CH4_FS_22050) && \ (I2S_CH4_1024FS != I2S_CH4_FS_22050) #error IOH_I2S_CH4_CONFIG Error : \ Sampling frequency 22050Hz can not generate. #endif #endif #ifdef I2S_CH4_FS_32000 #if (I2S_CH4_64FS != I2S_CH4_FS_32000) && \ (I2S_CH4_128FS != I2S_CH4_FS_32000) && \ (I2S_CH4_192FS != I2S_CH4_FS_32000) && \ (I2S_CH4_256FS != I2S_CH4_FS_32000) && \ (I2S_CH4_384FS != I2S_CH4_FS_32000) && \ (I2S_CH4_512FS != I2S_CH4_FS_32000) && \ (I2S_CH4_768FS != I2S_CH4_FS_32000) && \ (I2S_CH4_1024FS != I2S_CH4_FS_32000) #error IOH_I2S_CH4_CONFIG Error : \ Sampling frequency 32000Hz can not generate. #endif #endif #ifdef I2S_CH4_FS_44100 #if (I2S_CH4_64FS != I2S_CH4_FS_44100) && \ (I2S_CH4_128FS != I2S_CH4_FS_44100) && \ (I2S_CH4_192FS != I2S_CH4_FS_44100) && \ (I2S_CH4_256FS != I2S_CH4_FS_44100) && \ (I2S_CH4_384FS != I2S_CH4_FS_44100) && \ (I2S_CH4_512FS != I2S_CH4_FS_44100) && \ (I2S_CH4_768FS != I2S_CH4_FS_44100) && \ (I2S_CH4_1024FS != I2S_CH4_FS_44100) #error IOH_I2S_CH4_CONFIG Error : \ Sampling frequency 44100Hz can not generate. #endif #endif #ifdef I2S_CH4_FS_48000 #if (I2S_CH4_64FS != I2S_CH4_FS_48000) && \ (I2S_CH4_128FS != I2S_CH4_FS_48000) && \ (I2S_CH4_192FS != I2S_CH4_FS_48000) && \ (I2S_CH4_256FS != I2S_CH4_FS_48000) && \ (I2S_CH4_384FS != I2S_CH4_FS_48000) && \ (I2S_CH4_512FS != I2S_CH4_FS_48000) && \ (I2S_CH4_768FS != I2S_CH4_FS_48000) && \ (I2S_CH4_1024FS != I2S_CH4_FS_48000) #error IOH_I2S_CH4_CONFIG Error : \ Sampling frequency 48000Hz can not generate. #endif #endif #endif /* end of [#if (I2S_CH4_MSSEL == ioh_mssel_master)] */ /* ===== CH5 Parameter Error Check ==== */ #define USE_RATE_MAX_CH5 (0) #ifdef I2S_CH5_FS_8000 #define USE_RATE_CH5_8000 SNDRV_PCM_RATE_8000 #define USE_RATE_MIN_CH5 (8000) #if (USE_RATE_MAX_CH5 < 8000) #undef USE_RATE_MAX_CH5 #define USE_RATE_MAX_CH5 (8000) #endif #else #define USE_RATE_CH5_8000 0 #endif #ifdef I2S_CH5_FS_11025 #define USE_RATE_CH5_11025 SNDRV_PCM_RATE_11025 #ifndef USE_RATE_MIN_CH5 #define USE_RATE_MIN_CH5 (11025) #endif #if (USE_RATE_MAX_CH5 < 11025) #undef USE_RATE_MAX_CH5 #define USE_RATE_MAX_CH5 (11025) #endif #else #define USE_RATE_CH5_11025 0 #endif #ifdef I2S_CH5_FS_16000 #define USE_RATE_CH5_16000 SNDRV_PCM_RATE_16000 #ifndef USE_RATE_MIN_CH5 #define USE_RATE_MIN_CH5 (16000) #endif #if (USE_RATE_MAX_CH5 < 16000) #undef USE_RATE_MAX_CH5 #define USE_RATE_MAX_CH5 (16000) #endif #else #define USE_RATE_CH5_16000 0 #endif #ifdef I2S_CH5_FS_22050 #define USE_RATE_CH5_22050 SNDRV_PCM_RATE_22050 #ifndef USE_RATE_MIN_CH5 #define USE_RATE_MIN_CH5 (22050) #endif #if (USE_RATE_MAX_CH5 < 22050) #undef USE_RATE_MAX_CH5 #define USE_RATE_MAX_CH5 (22050) #endif #else #define USE_RATE_CH5_22050 0 #endif #ifdef I2S_CH5_FS_32000 #define USE_RATE_CH5_32000 SNDRV_PCM_RATE_32000 #ifndef USE_RATE_MIN_CH5 #define USE_RATE_MIN_CH5 (32000) #endif #if (USE_RATE_MAX_CH5 < 32000) #undef USE_RATE_MAX_CH5 #define USE_RATE_MAX_CH5 (32000) #endif #else #define USE_RATE_CH5_32000 0 #endif #ifdef I2S_CH5_FS_44100 #define USE_RATE_CH5_44100 SNDRV_PCM_RATE_44100 #ifndef USE_RATE_MIN_CH5 #define USE_RATE_MIN_CH5 (44100) #endif #if (USE_RATE_MAX_CH5 < 44100) #undef USE_RATE_MAX_CH5 #define USE_RATE_MAX_CH5 (44100) #endif #else #define USE_RATE_CH5_44100 0 #endif #ifdef I2S_CH5_FS_48000 #define USE_RATE_CH5_48000 SNDRV_PCM_RATE_48000 #ifndef USE_RATE_MIN_CH5 #define USE_RATE_MIN_CH5 (48000) #endif #if (USE_RATE_MAX_CH5 < 48000) #undef USE_RATE_MAX_CH5 #define USE_RATE_MAX_CH5 (48000) #endif #else #define USE_RATE_CH5_48000 0 #endif #define USE_RATE_CH5 (USE_RATE_CH5_8000|USE_RATE_CH5_11025 | \ USE_RATE_CH5_16000|USE_RATE_CH5_22050 | \ USE_RATE_CH5_32000|USE_RATE_CH5_44100 | \ USE_RATE_CH5_48000) #define I2S_CH5_64FS (I2S_CH5_MCLK/64) #define I2S_CH5_128FS (I2S_CH5_MCLK/128) #define I2S_CH5_192FS (I2S_CH5_MCLK/192) #define I2S_CH5_256FS (I2S_CH5_MCLK/256) #define I2S_CH5_384FS (I2S_CH5_MCLK/384) #define I2S_CH5_512FS (I2S_CH5_MCLK/512) #define I2S_CH5_768FS (I2S_CH5_MCLK/768) #define I2S_CH5_1024FS (I2S_CH5_MCLK/1024) #if (I2S_CH5_MSSEL == ioh_mssel_master) #ifdef I2S_CH5_FS_8000 #if (I2S_CH5_64FS != I2S_CH5_FS_8000) && \ (I2S_CH5_128FS != I2S_CH5_FS_8000) && \ (I2S_CH5_192FS != I2S_CH5_FS_8000) && \ (I2S_CH5_256FS != I2S_CH5_FS_8000) && \ (I2S_CH5_384FS != I2S_CH5_FS_8000) && \ (I2S_CH5_512FS != I2S_CH5_FS_8000) && \ (I2S_CH5_768FS != I2S_CH5_FS_8000) && \ (I2S_CH5_1024FS != I2S_CH5_FS_8000) #error IOH_I2S_CH5_CONFIG Error : \ Sampling frequency 8000Hz can not generate. #endif #endif #ifdef I2S_CH5_FS_11025 #if (I2S_CH5_64FS != I2S_CH5_FS_11025) && \ (I2S_CH5_128FS != I2S_CH5_FS_11025) && \ (I2S_CH5_192FS != I2S_CH5_FS_11025) && \ (I2S_CH5_256FS != I2S_CH5_FS_11025) && \ (I2S_CH5_384FS != I2S_CH5_FS_11025) && \ (I2S_CH5_512FS != I2S_CH5_FS_11025) && \ (I2S_CH5_768FS != I2S_CH5_FS_11025) && \ (I2S_CH5_1024FS != I2S_CH5_FS_11025) #error IOH_I2S_CH5_CONFIG Error : \ Sampling frequency 11025Hz can not generate. #endif #endif #ifdef I2S_CH5_FS_16000 #if (I2S_CH5_64FS != I2S_CH5_FS_16000) && \ (I2S_CH5_128FS != I2S_CH5_FS_16000) && \ (I2S_CH5_192FS != I2S_CH5_FS_16000) && \ (I2S_CH5_256FS != I2S_CH5_FS_16000) && \ (I2S_CH5_384FS != I2S_CH5_FS_16000) && \ (I2S_CH5_512FS != I2S_CH5_FS_16000) && \ (I2S_CH5_768FS != I2S_CH5_FS_16000) && \ (I2S_CH5_1024FS != I2S_CH5_FS_16000) #error IOH_I2S_CH5_CONFIG Error : \ Sampling frequency 16000Hz can not generate. #endif #endif #ifdef I2S_CH5_FS_22050 #if (I2S_CH5_64FS != I2S_CH5_FS_22050) && \ (I2S_CH5_128FS != I2S_CH5_FS_22050) && \ (I2S_CH5_192FS != I2S_CH5_FS_22050) && \ (I2S_CH5_256FS != I2S_CH5_FS_22050) && \ (I2S_CH5_384FS != I2S_CH5_FS_22050) && \ (I2S_CH5_512FS != I2S_CH5_FS_22050) && \ (I2S_CH5_768FS != I2S_CH5_FS_22050) && \ (I2S_CH5_1024FS != I2S_CH5_FS_22050) #error IOH_I2S_CH5_CONFIG Error : \ Sampling frequency 22050Hz can not generate. #endif #endif #ifdef I2S_CH5_FS_32000 #if (I2S_CH5_64FS != I2S_CH5_FS_32000) && \ (I2S_CH5_128FS != I2S_CH5_FS_32000) && \ (I2S_CH5_192FS != I2S_CH5_FS_32000) && \ (I2S_CH5_256FS != I2S_CH5_FS_32000) && \ (I2S_CH5_384FS != I2S_CH5_FS_32000) && \ (I2S_CH5_512FS != I2S_CH5_FS_32000) && \ (I2S_CH5_768FS != I2S_CH5_FS_32000) && \ (I2S_CH5_1024FS != I2S_CH5_FS_32000) #error IOH_I2S_CH5_CONFIG Error : \ Sampling frequency 32000Hz can not generate. #endif #endif #ifdef I2S_CH5_FS_44100 #if (I2S_CH5_64FS != I2S_CH5_FS_44100) && \ (I2S_CH5_128FS != I2S_CH5_FS_44100) && \ (I2S_CH5_192FS != I2S_CH5_FS_44100) && \ (I2S_CH5_256FS != I2S_CH5_FS_44100) && \ (I2S_CH5_384FS != I2S_CH5_FS_44100) && \ (I2S_CH5_512FS != I2S_CH5_FS_44100) && \ (I2S_CH5_768FS != I2S_CH5_FS_44100) && \ (I2S_CH5_1024FS != I2S_CH5_FS_44100) #error IOH_I2S_CH5_CONFIG Error : \ Sampling frequency 44100Hz can not generate. #endif #endif #ifdef I2S_CH5_FS_48000 #if (I2S_CH5_64FS != I2S_CH5_FS_48000) && \ (I2S_CH5_128FS != I2S_CH5_FS_48000) && \ (I2S_CH5_192FS != I2S_CH5_FS_48000) && \ (I2S_CH5_256FS != I2S_CH5_FS_48000) && \ (I2S_CH5_384FS != I2S_CH5_FS_48000) && \ (I2S_CH5_512FS != I2S_CH5_FS_48000) && \ (I2S_CH5_768FS != I2S_CH5_FS_48000) && \ (I2S_CH5_1024FS != I2S_CH5_FS_48000) #error IOH_I2S_CH5_CONFIG Error : \ Sampling frequency 48000Hz can not generate. #endif #endif #endif /* end of [#if (I2S_CH5_MSSEL == ioh_mssel_master)] */ /* ######################################################################## */ /* ### Parameter Table Data ### */ /* ######################################################################## */ #define I2SCLKCNT_MSSEL_OFFSET (0) #define I2SCLKCNT_BCLKPOL_OFFSET (1) #define I2SCLKCNT_MASTERCLKSEL_OFFSET (2) #define I2SCLKCNT_LRCKFMT_OFFSET (4) #define I2SCLKCNT_MCLKFS_OFFSET (8) #define I2SCLKCNT_BCLKFS_OFFSET (12) #define I2SCNT_DABIT_OFFSET (8) #define I2SCNTTX_TX_TEL_OFFSET (0) #define I2SCNTTX_TX_DLYOFF_OFFSET (12) #define I2SCNTTX_TX_LSB_OFFSET (13) #define I2SCNTTX_TX_LRPOL_OFFSET (14) #define I2SCNTTX_TX_AFT_OFFSET (15) #define I2SCNTRX_RX_TEL_OFFSET (0) #define I2SCNTRX_RX_DLYOFF_OFFSET (12) #define I2SCNTRX_RX_LSB_OFFSET (13) #define I2SCNTRX_RX_LRPOL_OFFSET (14) #define I2SCNTRX_RX_AFT_OFFSET (15) #define STEREO_OFFSET 0 #define MONAURAL_OFFSET MAX_I2S_CH static const struct i2s_config_tab_t i2s_config_table[MAX_I2S_CH*2] = { /* CH0 Stereo */ { (I2S_CH0_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH0_BCLKPOL_STEREO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH0_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH0_LRCKFMT_STEREO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH0_TX_DLYOFF_STEREO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH0_TX_LSB_STEREO << I2SCNTTX_TX_LSB_OFFSET) | \ (I2S_CH0_TX_LRPOL_STEREO << I2SCNTTX_TX_LRPOL_OFFSET) | \ (I2S_CH0_TX_AFT_STEREO << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH0_RX_DLYOFF_STEREO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH0_RX_LSB_STEREO << I2SCNTRX_RX_LSB_OFFSET) | \ (I2S_CH0_RX_LRPOL_STEREO << I2SCNTRX_RX_LRPOL_OFFSET) | \ (I2S_CH0_RX_AFT_STEREO << I2SCNTRX_RX_AFT_OFFSET), I2S_CH0_MCLK, }, /* CH1 Stereo */ { (I2S_CH1_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH1_BCLKPOL_STEREO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH1_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH1_LRCKFMT_STEREO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH1_TX_DLYOFF_STEREO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH1_TX_LSB_STEREO << I2SCNTTX_TX_LSB_OFFSET) | \ (I2S_CH1_TX_LRPOL_STEREO << I2SCNTTX_TX_LRPOL_OFFSET) | \ (I2S_CH1_TX_AFT_STEREO << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH1_RX_DLYOFF_STEREO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH1_RX_LSB_STEREO << I2SCNTRX_RX_LSB_OFFSET) | \ (I2S_CH1_RX_LRPOL_STEREO << I2SCNTRX_RX_LRPOL_OFFSET) | \ (I2S_CH1_RX_AFT_STEREO << I2SCNTRX_RX_AFT_OFFSET), I2S_CH1_MCLK, }, /* CH2 Stereo */ { (I2S_CH2_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH2_BCLKPOL_STEREO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH2_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH2_LRCKFMT_STEREO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH2_TX_DLYOFF_STEREO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH2_TX_LSB_STEREO << I2SCNTTX_TX_LSB_OFFSET) | \ (I2S_CH2_TX_LRPOL_STEREO << I2SCNTTX_TX_LRPOL_OFFSET) | \ (I2S_CH2_TX_AFT_STEREO << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH2_RX_DLYOFF_STEREO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH2_RX_LSB_STEREO << I2SCNTRX_RX_LSB_OFFSET) | \ (I2S_CH2_RX_LRPOL_STEREO << I2SCNTRX_RX_LRPOL_OFFSET) | \ (I2S_CH2_RX_AFT_STEREO << I2SCNTRX_RX_AFT_OFFSET), I2S_CH2_MCLK, }, /* CH3 Stereo */ { (I2S_CH3_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH3_BCLKPOL_STEREO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH3_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH3_LRCKFMT_STEREO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH3_TX_DLYOFF_STEREO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH3_TX_LSB_STEREO << I2SCNTTX_TX_LSB_OFFSET) | \ (I2S_CH3_TX_LRPOL_STEREO << I2SCNTTX_TX_LRPOL_OFFSET) | \ (I2S_CH3_TX_AFT_STEREO << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH3_RX_DLYOFF_STEREO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH3_RX_LSB_STEREO << I2SCNTRX_RX_LSB_OFFSET) | \ (I2S_CH3_RX_LRPOL_STEREO << I2SCNTRX_RX_LRPOL_OFFSET) | \ (I2S_CH3_RX_AFT_STEREO << I2SCNTRX_RX_AFT_OFFSET), I2S_CH3_MCLK, }, /* CH4 Stereo */ { (I2S_CH4_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH4_BCLKPOL_STEREO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH4_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH4_LRCKFMT_STEREO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH4_TX_DLYOFF_STEREO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH4_TX_LSB_STEREO << I2SCNTTX_TX_LSB_OFFSET) | \ (I2S_CH4_TX_LRPOL_STEREO << I2SCNTTX_TX_LRPOL_OFFSET) | \ (I2S_CH4_TX_AFT_STEREO << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH4_RX_DLYOFF_STEREO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH4_RX_LSB_STEREO << I2SCNTRX_RX_LSB_OFFSET) | \ (I2S_CH4_RX_LRPOL_STEREO << I2SCNTRX_RX_LRPOL_OFFSET) | \ (I2S_CH4_RX_AFT_STEREO << I2SCNTRX_RX_AFT_OFFSET), I2S_CH4_MCLK, }, /* CH5 Stereo */ { (I2S_CH5_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH5_BCLKPOL_STEREO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH5_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH5_LRCKFMT_STEREO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH5_TX_DLYOFF_STEREO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH5_TX_LSB_STEREO << I2SCNTTX_TX_LSB_OFFSET) | \ (I2S_CH5_TX_LRPOL_STEREO << I2SCNTTX_TX_LRPOL_OFFSET) | \ (I2S_CH5_TX_AFT_STEREO << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH5_RX_DLYOFF_STEREO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH5_RX_LSB_STEREO << I2SCNTRX_RX_LSB_OFFSET) | \ (I2S_CH5_RX_LRPOL_STEREO << I2SCNTRX_RX_LRPOL_OFFSET) | \ (I2S_CH5_RX_AFT_STEREO << I2SCNTRX_RX_AFT_OFFSET), I2S_CH5_MCLK, }, /* CH0 Mono */ { (I2S_CH0_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH0_BCLKPOL_MONO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH0_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH0_LRCKFMT_MONO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH0_TX_DLYOFF_MONO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH0_TX_LSB_MONO << I2SCNTTX_TX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTTX_TX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH0_RX_DLYOFF_MONO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH0_RX_LSB_MONO << I2SCNTRX_RX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTRX_RX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTRX_RX_AFT_OFFSET), I2S_CH0_MCLK, }, /* CH1 Mono */ { (I2S_CH1_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH1_BCLKPOL_MONO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH1_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH1_LRCKFMT_MONO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH1_TX_DLYOFF_MONO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH1_TX_LSB_MONO << I2SCNTTX_TX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTTX_TX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH1_RX_DLYOFF_MONO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH1_RX_LSB_MONO << I2SCNTRX_RX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTRX_RX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTRX_RX_AFT_OFFSET), I2S_CH1_MCLK, }, /* CH2 Mono */ { (I2S_CH2_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH2_BCLKPOL_MONO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH2_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH2_LRCKFMT_MONO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH2_TX_DLYOFF_MONO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH2_TX_LSB_MONO << I2SCNTTX_TX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTTX_TX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH2_RX_DLYOFF_MONO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH2_RX_LSB_MONO << I2SCNTRX_RX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTRX_RX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTRX_RX_AFT_OFFSET), I2S_CH2_MCLK, }, /* CH3 Mono */ { (I2S_CH3_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH3_BCLKPOL_MONO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH3_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH3_LRCKFMT_MONO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH3_TX_DLYOFF_MONO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH3_TX_LSB_MONO << I2SCNTTX_TX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTTX_TX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH3_RX_DLYOFF_MONO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH3_RX_LSB_MONO << I2SCNTRX_RX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTRX_RX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTRX_RX_AFT_OFFSET), I2S_CH3_MCLK, }, /* CH4 Mono */ { (I2S_CH4_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH4_BCLKPOL_MONO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH4_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH4_LRCKFMT_MONO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH4_TX_DLYOFF_MONO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH4_TX_LSB_MONO << I2SCNTTX_TX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTTX_TX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH4_RX_DLYOFF_MONO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH4_RX_LSB_MONO << I2SCNTRX_RX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTRX_RX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTRX_RX_AFT_OFFSET), I2S_CH4_MCLK, }, /* CH5 Mono */ { (I2S_CH5_MSSEL << I2SCLKCNT_MSSEL_OFFSET) | \ (I2S_CH5_BCLKPOL_MONO << I2SCLKCNT_BCLKPOL_OFFSET) | \ (I2S_CH5_MASTERCLKSEL << I2SCLKCNT_MASTERCLKSEL_OFFSET) | \ (I2S_CH5_LRCKFMT_MONO << I2SCLKCNT_LRCKFMT_OFFSET), (I2S_CH5_TX_DLYOFF_MONO << I2SCNTTX_TX_DLYOFF_OFFSET) | \ (I2S_CH5_TX_LSB_MONO << I2SCNTTX_TX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTTX_TX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTTX_TX_AFT_OFFSET), (I2S_CH5_RX_DLYOFF_MONO << I2SCNTRX_RX_DLYOFF_OFFSET) | \ (I2S_CH5_RX_LSB_MONO << I2SCNTRX_RX_LSB_OFFSET) | \ (ioh_lrpol_no_invert << I2SCNTRX_RX_LRPOL_OFFSET) | \ (ioh_aft_front << I2SCNTRX_RX_AFT_OFFSET), I2S_CH5_MCLK, }, }; #endif