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Message-ID: <20111108141825.GQ3225@redhat.com>
Date: Tue, 8 Nov 2011 16:18:25 +0200
From: Gleb Natapov <gleb@...hat.com>
To: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc: kvm@...r.kernel.org, avi@...hat.com, mtosatti@...hat.com,
linux-kernel@...r.kernel.org, mingo@...e.hu,
acme@...stprotocols.net
Subject: Re: [PATCHv2 6/9] perf: expose perf capability to other modules.
On Tue, Nov 08, 2011 at 03:12:27PM +0100, Peter Zijlstra wrote:
> On Tue, 2011-11-08 at 15:54 +0200, Gleb Natapov wrote:
> > Isn't it better to introduce mapping between ebx bits and architectural
> > events and do for_each_set_bit loop?
>
> Probably, but I only thought of that halfway through ;-)
>
> > But I wouldn't want to introduce
> > patch as below as part of this series.
>
> Well, since you're actually going to frob cpuid10.ebx bits we had better
> deal with it properly.
OK. We need to figure what is the proper way though. How about me
introducing cpuid10_ebx with event_mask bitmask, mapping array, but
not disabling events for now.
>
> > I do not want to introduce
> > incidental regressions. For instance the patch below will introduce
> > regression on my Nehalem cpu. It reports value 0x44 in cpuid10.ebx which
> > means that unhalted_reference_cycles is not available (bit set means
> > event is not available), but event still works! Actually it is listed as
> > supported by the cpu in Table A-4 SDM 3B. Go figure.
>
> We'd better figure out why your machine says that. It could be we need
> another quirk for the nehalem machines, it could be your BIOS is smoking
> crack and there's nothing we can do about it.
>
I asked Intel a week (or so) ago. Waiting for an answer. Will try to
find other machines with similar cpu to do more checks meanwhile.
--
Gleb.
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