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Message-ID: <20111108171725.GE5182@amd.com>
Date:	Tue, 8 Nov 2011 18:17:25 +0100
From:	"Roedel, Joerg" <Joerg.Roedel@....com>
To:	Alex Williamson <alex.williamson@...hat.com>
CC:	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"jbarnes@...tuousgeek.org" <jbarnes@...tuousgeek.org>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>
Subject: Re: [PATCH] pci: More PRI/PASID cleanup

On Tue, Nov 08, 2011 at 09:44:30AM -0700, Alex Williamson wrote:

> bit 0 (PCI_PASID_ENABLE) is reserved in the CAP register...

Is it? Which spec are you using? In my version it is not reserved but
states if it is supported to set the enable-bit.

> Which means we need to check CTRL, not CAP to see if it was previously
> enabled... or maybe this check is entirely wrong and we're was trying to
> see if enable is supported.

I will check how this looks in my test environment.

> And nobody exposes PCI_PASID_ENABLE because it doesn't exist as a
> capability.
> 
> It's easy to see this if the bit definitions are named appropriately and
> specified per register instead of being lumped together as "close
> enough".  Thanks,

I don't object against your renames as long as it doesn't cause
merge-conflicts with what I plan to send upstream.

Thanks,

	Joerg

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