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Message-ID: <4567A1A9-51D2-4D21-9080-BD3D78901C1D@boeing.com>
Date:	Thu, 10 Nov 2011 14:27:35 -0600
From:	"Moffett, Kyle D" <Kyle.D.Moffett@...ing.com>
To:	Scott Wood <scottwood@...escale.com>
CC:	Kumar Gala <galak@...nel.crashing.org>,
	"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Baruch Siach <baruch@...s.co.il>,
	Timur Tabi <B04825@...escale.com>,
	Paul Gortmaker <paul.gortmaker@...driver.com>,
	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	Paul Mackerras <paulus@...ba.org>
Subject: Re: [RFC PATCH 08/17] powerpc/e500: Remove conditional "lwsync"
 substitution

On Nov 10, 2011, at 12:03, Scott Wood wrote:
> On Thu, Nov 10, 2011 at 10:42:25AM -0600, Kumar Gala wrote:
>> 
>> On Nov 10, 2011, at 10:31 AM, Scott Wood wrote:
>> 
>>> On Thu, Nov 10, 2011 at 07:40:04AM -0600, Kumar Gala wrote:
>>>> Nak, we can run an e500mc in a mode that is compatible with e500v1/v2.
>>>> I see no reason to change the support we have there.
>>> 
>>> What "mode" do you mean?  DCBZ32?  We don't support using that currently,
>>> and I'd imagine the performance implication would be such that you'd
>>> never want to do it unless it's the only way to make some piece of legacy
>>> software work.
>> 
>> Correct, DCBZ32, we've had customers that go down this path.
> 
> For running legacy software, or for multiplatform Linux kernels?
> 
> And if you're willing to toss performance away for this goal, why do you
> need lwsync? :-)
> 
> DCBZ32 is not a "mode that is compatible with v1/v2", BTW.  It only
> affects cache block size (for dcbz/dcba only), not SPE versus FP, not
> changes in power management, not changes in machine check handling, etc.
> 
> Using DCBZ32 for the kernel would also complicate switching the kernel to
> dcbzl, to support enabling DCBZ32 for certain userspace apps (a more
> likely use case) without making it systemwide.

So, as far as I can tell the kernel doesn't even try to touch DCBZ32.

Even if it did, if you are building a new kernel that includes this patch,
surely you can actually build a proper e500mc kernel instead of trying to
build a new kernel to run on hardware it wasn't designed to run on, right?

I think the bigger issue is the fact that building a PPC_BOOK3E_64 kernel
with both e5500 and PowerPC A2 support turned on will not actually run on
both.  Before my v1-patch-series, machine-check handling is messed up for
PowerPC A2, and afterwards cacheline sizes are messed up for e5500.

Does this mean that PPC_BOOK3E_64 needs to be split into two separate
Book 3-III families the same way that 32-bit has been split?  Is there
another way around it?

Cheers,
Kyle Moffett
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