linux-kernel - Re: [PATCH] intel-iommu: Default to non-coherent for domains unattached to iommus

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Message-ID: <1321059340.2006.27.camel@shinybook.infradead.org>
Date:	Sat, 12 Nov 2011 00:55:40 +0000
From:	David Woodhouse <dwmw2@...radead.org>
To:	Chris Wright <chrisw@...s-sol.org>
Cc:	Roland Dreier <roland@...estorage.com>,
	Alex Williamson <alex.williamson@...hat.com>,
	iommu@...ts.linux-foundation.org, linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org, ddutile@...hat.com
Subject: Re: [PATCH] intel-iommu: Default to non-coherent for domains
 unattached to iommus

On Fri, 2011-11-11 at 16:51 -0800, Chris Wright wrote:
> * Roland Dreier (roland@...estorage.com) wrote:
> > On Fri, Nov 11, 2011 at 4:37 PM, David Woodhouse <dwmw2@...radead.org> wrote:
> > > This brain-damage only affects the first chipsets
> > > from before we worked out that cache incoherency was a *really* f*cking
> > > stupid idea, doesn't it?
> > 
> > As we talked about at KS, I have some Westmere EP (ie latest
> > and greatest server platform) systems where the BIOS exposes
> > an option that allows choosing VT-d coherency on or off, and
> > defaults it to "off".
> 
> That's just more brain damage AFAICT.  Esp. if you do performance
> testing (and choose not to use passthrough mode)... have and it's
> quite measurable.  I switched default to on long time ago, w/out
> issue.
> 
> > What is the "official" Intel line on coherency with Westmere and
> > Tylersburg -- because as I also mentioned, I was seeing some
> > problems with VT-d and the default "coherency off" setting that
> > looked like the IOMMU HW is getting stale PTEs (ie a missing
> > or not working cache flush).
> 
> That sounds like sw bugs more than official recommendation issue.

Although the cache-flushing has been tested on the original chipsets
fairly well, and it's one of the parts I've mostly rewritten when doing
performance work since I inherited the code, so that might not be my
first suspicion. I would be more inclined to suspect that there's some
chipset buffering that we aren't correctly flushing (which might in
itself be a hardware issue, since the way to flush the cache is supposed
to be well-defined).

-- 
dwmw2

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