linux-kernel - [14/26] drm/i915: enable ring freq scaling, RC6 and graphics turbo on Ivy Bridge v3

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Date:	Fri, 18 Nov 2011 15:58:27 -0800
From:	Greg KH <gregkh@...e.de>
To:	linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc:	torvalds@...ux-foundation.org, akpm@...ux-foundation.org,
	alan@...rguk.ukuu.org.uk, Jesse Barnes <jbarnes@...tuousgeek.org>,
	Keith Packard <keithp@...thp.com>,
	Robert Hooker <robert.hooker@...onical.com>,
	Leann Ogasawara <leann.ogasawara@...onical.com>,
	Herton Krzesinski <herton.krzesinski@...onical.com>,
	Tim Gardner <tim.gardner@...onical.com>
Subject: [14/26] drm/i915: enable ring freq scaling, RC6 and graphics turbo on Ivy Bridge v3

3.0-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Jesse Barnes <jbarnes@...tuousgeek.org>

commit 1c70c0cebd1295a42fec75045b8a6b4419cedef3 upstream.

They use the same register interfaces, so we can simply enable the
existing code on IVB.

v2:
  - resolve conflict with ring freq scaling, we can enable it too
v3:
  - resolve conflict again, this time on drm-intel-next

Signed-off-by: Jesse Barnes <jbarnes@...tuousgeek.org>
Signed-off-by: Keith Packard <keithp@...thp.com>
Signed-off-by: Robert Hooker <robert.hooker@...onical.com>
Acked-by: Leann Ogasawara <leann.ogasawara@...onical.com>
Acked-by: Herton Krzesinski <herton.krzesinski@...onical.com>
Signed-off-by: Tim Gardner <tim.gardner@...onical.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...e.de>

---
 drivers/gpu/drm/i915/i915_debugfs.c  |    2 +-
 drivers/gpu/drm/i915/intel_display.c |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -865,7 +865,7 @@ static int i915_cur_delayinfo(struct seq
 			   MEMSTAT_VID_SHIFT);
 		seq_printf(m, "Current P-state: %d\n",
 			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
-	} else if (IS_GEN6(dev)) {
+	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
 		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7943,7 +7943,7 @@ void intel_modeset_init(struct drm_devic
 		intel_init_emon(dev);
 	}
 
-	if (IS_GEN6(dev))
+	if (IS_GEN6(dev) || IS_GEN7(dev))
 		gen6_enable_rps(dev_priv);
 
 	INIT_WORK(&dev_priv->idle_work, intel_idle_update);
@@ -7985,7 +7985,7 @@ void intel_modeset_cleanup(struct drm_de
 
 	if (IS_IRONLAKE_M(dev))
 		ironlake_disable_drps(dev);
-	if (IS_GEN6(dev))
+	if (IS_GEN6(dev) || IS_GEN7(dev))
 		gen6_disable_rps(dev);
 
 	if (IS_IRONLAKE_M(dev))


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