linux-kernel - Re: [PATCH v3 4/5] clk: basic gateable and fixed-rate clks

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Message-ID: <20111126134807.GD19025@S2100-06.ap.freescale.net>
Date:	Sat, 26 Nov 2011 21:48:08 +0800
From:	Shawn Guo <shawn.guo@...escale.com>
To:	Mike Turquette <mturquette@...com>
CC:	<linux@....linux.org.uk>, <linux-kernel@...r.kernel.org>,
	<linux-omap@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<jeremy.kerr@...onical.com>, <broonie@...nsource.wolfsonmicro.com>,
	<tglx@...utronix.de>, <linus.walleij@...ricsson.com>,
	<amit.kucheria@...aro.org>, <dsaxena@...aro.org>,
	<patches@...aro.org>, <linaro-dev@...ts.linaro.org>,
	<aul@...an.com>, <grant.likely@...retlab.ca>, <sboyd@...cinc.com>,
	<skannan@...cinc.com>, <magnus.damm@...il.com>,
	<arnd.bergmann@...aro.org>, <eric.miao@...aro.org>,
	<richard.zhao@...aro.org>, Mike Turquette <mturquette@...aro.org>
Subject: Re: [PATCH v3 4/5] clk: basic gateable and fixed-rate clks

On Mon, Nov 21, 2011 at 05:40:46PM -0800, Mike Turquette wrote:
> Many platforms support simple gateable clks and fixed-rate clks that
> should not be re-implemented by every platform.
> 
> This patch introduces a gateable clk with a common programming model of
> gate control via a write of 1 bit to a register.  Both set-to-enable and
> clear-to-enable are supported.
> 
> Also introduced is a fixed-rate clk which has no reprogrammable aspects.
> 
> The purpose of both types of clks is documented in drivers/clk/basic.c.
> 
What I have seen is drivers/clk/clk-basic.c.

> TODO: add support for a simple divider, simple mux and a dummy clk for
> stubbing out platform support.
> 
> Based on original patch by Jeremy Kerr contribution by Jamie Iles.
> 
> Signed-off-by: Mike Turquette <mturquette@...aro.org>
> ---
>  drivers/clk/Kconfig     |    7 ++
>  drivers/clk/Makefile    |    5 +-
>  drivers/clk/clk-basic.c |  208 +++++++++++++++++++++++++++++++++++++++++++++++
>  include/linux/clk.h     |   35 ++++++++
>  4 files changed, 253 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/clk/clk-basic.c

[...]

> +int clk_register_gate(struct device *dev, const char *name, unsigned long flags,
> +		struct clk *fixed_parent, void __iomem *reg, u8 bit_idx,
> +		int set_to_enable)
> +{
> +	struct clk_hw_gate *gclk;
> +	struct clk *clk;
> +
> +	gclk = kmalloc(sizeof(struct clk_hw_gate), GFP_KERNEL);
> +
> +	if (!gclk) {
> +		pr_err("%s: could not allocate gated clk\n", __func__);
> +		return -ENOMEM;
> +	}
> +
> +	clk = &gclk->clk;
> +
> +	/* struct clk_hw_gate assignments */
> +	gclk->fixed_parent = fixed_parent;
> +	gclk->reg = reg;
> +	gclk->bit_idx = bit_idx;
> +
> +	/* struct clk assignments */
> +	clk->name = name;
> +	clk->flags = flags;
> +
> +	if (set_to_enable)
> +		clk->ops = &clk_hw_gate_set_enable_ops;
> +	else
> +		clk->ops = &clk_hw_gate_set_disable_ops;
> +
> +	clk_init(NULL, clk);
> +
> +	return 0;

The device tree support needs to get this 'struct clk *', so we may
want to have all these registering functions return the 'clk'.

> +}

-- 
Regards,
Shawn

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