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Message-ID: <1323124508.32012.46.camel@twins>
Date: Mon, 05 Dec 2011 23:35:08 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Stephane Eranian <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org, mingo@...e.hu, acme@...hat.com,
ming.m.lin@...el.com, andi@...stfloor.org, robert.richter@....com,
ravitillo@....gov, will.deacon@....com, paulus@...ba.org,
benh@...nel.crashing.org, rth@...ddle.net, ralf@...ux-mips.org,
davem@...emloft.net, lethal@...ux-sh.org
Subject: Re: [PATCH 05/12] perf_events: add LBR mappings for
PERF_SAMPLE_BRANCH filters (v2)
On Fri, 2011-10-14 at 14:37 +0200, Stephane Eranian wrote:
> void intel_pmu_lbr_init_atom(void)
> {
> + /*
> + * only models starting at stepping 10 seems
> + * to have an operational LBR which can freeze
> + * on PMU interrupt
> + */
> + if (boot_cpu_data.x86_mask < 10) {
> + pr_cont("LBR disabled due to erratum");
> + return;
> + }
Shouldn't that be a separate patch?
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