| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Fri, 9 Dec 2011 18:07:20 +0100 From: Wolfram Sang <w.sang@...gutronix.de> To: linux-serial@...r.kernel.org Cc: linux-kernel@...r.kernel.org, Greg KH <gregkh@...e.de>, Alan Cox <alan@...ux.intel.com>, Claudio Scordino <claudio@...dence.eu.com>, Wolfram Sang <w.sang@...gutronix.de> Subject: [PATCH RESEND 8/8] serial: 8250: fix comment about accessing EMSR All docs I checked do say LCR should NOT be 0xBF (16c850, 16c854, 16v2750). Fix it according to that, since the only usage of the register currently implements the revised access method. If somebody later finds a derivate which actually does need 0xBF to enable that register, we can update the comment again with precise references. Signed-off-by: Wolfram Sang <w.sang@...gutronix.de> --- include/linux/serial_reg.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index 0267bab6..0a1beca 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -211,7 +211,7 @@ #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ /* - * LCR=0xBF, FCTR[6]=1 + * LCR!=0xBF (some docs say =0), FCTR[6]=1, XR16C85x */ #define UART_EMSR 7 /* Extended Mode Select Register */ #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ -- 1.7.7.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists