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Message-ID: <20111209174911.GD14900@aftab>
Date: Fri, 9 Dec 2011 18:49:11 +0100
From: Borislav Petkov <bp@...64.org>
To: Steven Rostedt <rostedt@...dmis.org>
Cc: linux-kernel@...r.kernel.org, Ingo Molnar <mingo@...e.hu>,
Andrew Morton <akpm@...ux-foundation.org>,
Thomas Gleixner <tglx@...utronix.de>,
Peter Zijlstra <peterz@...radead.org>,
Linus Torvalds <torvalds@...ux-foundation.org>,
"H. Peter Anvin" <hpa@...or.com>,
Frederic Weisbecker <fweisbec@...il.com>,
Jason Baron <jbaron@...hat.com>,
Mathieu Desnoyers <mathieu.desnoyers@...icios.com>,
"H. Peter Anvin" <hpa@...ux.intel.com>,
Paul Turner <pjt@...gle.com>, Borislav Petkov <bp@...64.org>
Subject: Re: [RFC][PATCH 3/3] x86: Add workaround to NMI iret woes
Hey Steve,
On Fri, Dec 09, 2011 at 12:19:31PM -0500, Steven Rostedt wrote:
> Could you shed some light on this. Can an NMI interrupt an MCE in
> progress?
Easy, http://support.amd.com/us/Processor_TechDocs/APM_V2_24593.pdf,
section 8.5.
On amd64 #MC is along with processor reset the highest prio. Judging
from the text, an NMI occurring during an #MC is held until we return
from the #MC handler:
"When simultaneous interrupts occur, the processor transfers control
to the highest-priority interrupt handler. Lower-priority interrupts
from external sources are held pending by the processor, and they are
handled after the higher-priority interrupt is handled. Lower-priority
interrupts that result from internal sources are discarded. Those
interrupts reoccur when the high-priority interrupt handler completes
and transfers control back to the interrupted instruction."
HTH.
--
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