lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Date:	Sun, 11 Dec 2011 00:28:50 +0100
From:	Stephane Eranian <eranian@...gle.com>
To:	linux-kernel@...r.kernel.org
Cc:	peterz@...radead.org, mingo@...e.hu, acme@...radead.org,
	robert.richter@....com, ming.m.lin@...el.com, andi@...stfloor.org,
	asharma@...com
Subject: [PATCH 0/4] perf_events: add support for Intel reference cycles event

The unhalted_reference_cycles is a very useful event which counts cycles at the
reference CPU clock speed (same as TSC if processors supports constant_tsc).
That means, it keeps a constant correlation with wall-clock time while the
processor is not halted, unlike its counter-part unhalted_core_cycles.
The latter event, used by generic PMU event cycles in the perf tool is
subject to frequency down-scaling AND Turbo mode fluctuations.

The unhlated_reference_cycles is NOT equivalent to wall clock time because
it counts only when the processor is not in halted state. But this limitation
impacts only system-wide measurements.

The unhalted_reference_cycles can only be counted on fixed counter 2.
As such, it does not have an event encoding. Fixed counters can only measure
one (hardwired) event. Yet, with perf_events user manipulates events and not
counters, thus each event needs an encoding. That encoding is then used by
the kernel to identify the event and schedule it on the proper counter.

Up until now, there was no encoding chosen for unhalted_reference_cycles, thus
it could not be scheduled properly and thus it was not supported.

This patch uses the encoding 0x0300. That means event code 0x00, umask 0x3.
That event code is not used by Intel on any existing processor. We have
also checked with Intel and it seems that they don't plan on using it in
the future.

With this patch, it is possible to see the effect of Turbo mode:

$ perf stat -e unhalted_reference_cycles,unhalted_core_cycles ./noploop 1
noploop for 1 seconds

Performance counter stats for './noploop 1':

3,197,640,960 unhalted_reference_cycles
3,595,043,997 unhalted_core_cycles

1.000732233  seconds time elapsed

Signed-off-by: Stephane Eranian <eranian@...gle.com>
---

Stephane Eranian (4):
  perf_events: enable raw event support for Intel
    unhalted_reference_cycles event
  perf_event: add PERF_COUNT_HW_REF_CPU_CYCLES generic PMU event
  perf_events: add Intel X86 mapping for PERF_COUNT_HW_REF_CPU_CYCLES
  perf: add support for PERF_HW_COUNT_REF_CPU_CYCLES

 arch/x86/include/asm/perf_event.h      |   15 ++++++++-------
 arch/x86/kernel/cpu/perf_event.c       |    8 +++++++-
 arch/x86/kernel/cpu/perf_event_intel.c |   16 ++++++----------
 include/linux/perf_event.h             |    1 +
 tools/perf/util/parse-events.c         |    2 ++
 5 files changed, 24 insertions(+), 18 deletions(-)

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ