linux-kernel - [PATVCH V3 Resend 5/5] gpio/gpio-stmpe: ADD support for stmpe variant 801

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Message-ID: <3acffb8a1da1ff69d70e745b23e8b79a859586c2.1321507421.git.viresh.kumar@st.com>
Date:	Wed, 14 Dec 2011 09:28:27 +0530
From:	Viresh Kumar <viresh.kumar@...com>
To:	<sameo@...ux.intel.com>
Cc:	<rabin.vincent@...ricsson.com>, <linus.walleij@...ricsson.com>,
	<srinidhi.kasagar@...ricsson.com>, <armando.visconti@...com>,
	<shiraz.hashim@...com>, <vipin.kumar@...com>,
	<rajeev-dlh.kumar@...com>, <deepak.sikri@...com>,
	<vipulkumar.samar@...com>, <amit.virdi@...com>,
	<viresh.kumar@...com>, <pratyush.anand@...com>,
	<bhupesh.sharma@...com>, <viresh.linux@...il.com>,
	<bhavna.yadav@...com>, <vincenzo.frascino@...com>,
	<mirko.gardi@...com>, <grant.likely@...retlab.ca>,
	<linux-kernel@...r.kernel.org>
Subject: [PATVCH V3 Resend 5/5] gpio/gpio-stmpe: ADD support for stmpe variant 801

STMPE801 is a GPIO expander. GPIO registers for 801 are slightly different from other
variants. This patch adds support for STMPE801 in stmpe gpio driver.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...com>
Signed-off-by: Pratyush Anand <pratyush.anand@...com>
Signed-off-by: Viresh Kumar <viresh.kumar@...com>
---

Hi Samuel,

Please apply this patch instead of V2 5/5.

Changes since V2:
- stmpe_gpio_set() is updates, so that it doesn't configure other gpio pins by
  mistake.
- STMPE801 also supports Edge interrupts and not level ints. Code updated
  for this too.

 drivers/gpio/gpio-stmpe.c |   25 ++++++++++++++++++++++---
 1 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index 4c980b5..87a68a8 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -65,7 +65,14 @@ static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
 	u8 reg = stmpe->regs[which] - (offset / 8);
 	u8 mask = 1 << (offset % 8);
 
-	stmpe_reg_write(stmpe, reg, mask);
+	/*
+	 * Some variants have single register for gpio set/clear functionality.
+	 * For them we need to write 0 to clear and 1 to set.
+	 */
+	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
+		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
+	else
+		stmpe_reg_write(stmpe, reg, mask);
 }
 
 static int stmpe_gpio_direction_output(struct gpio_chip *chip,
@@ -132,6 +139,10 @@ static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
 		return -EINVAL;
 
+	/* STMPE801 doesn't have RE and FE registers */
+	if (stmpe_gpio->stmpe->partnum == STMPE801)
+		return 0;
+
 	if (type == IRQ_TYPE_EDGE_RISING)
 		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
 	else
@@ -165,6 +176,11 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
 	int i, j;
 
 	for (i = 0; i < CACHE_NR_REGS; i++) {
+		/* STMPE801 doesn't have RE and FE registers */
+		if ((stmpe->partnum == STMPE801) &&
+				(i != REG_IE))
+			continue;
+
 		for (j = 0; j < num_banks; j++) {
 			u8 old = stmpe_gpio->oldregs[i][j];
 			u8 new = stmpe_gpio->regs[i][j];
@@ -241,8 +257,11 @@ static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
 		}
 
 		stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
-		stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
-				status[i]);
+
+		/* Edge detect register is not present on 801 */
+		if (stmpe->partnum != STMPE801)
+			stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
+					+ i, status[i]);
 	}
 
 	return IRQ_HANDLED;
-- 
1.7.8.110.g4cb5d

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