lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20111216213634.GA25241@arm.com>
Date:	Fri, 16 Dec 2011 21:36:34 +0000
From:	Catalin Marinas <catalin.marinas@....com>
To:	Frank Rowand <frank.rowand@...sony.com>
Cc:	"Rowand, Frank" <Frank_Rowand@...yusa.com>,
	"tglx@...utronix.de" <tglx@...utronix.de>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"peterz@...radead.org" <peterz@...radead.org>,
	"rostedt@...dmis.org" <rostedt@...dmis.org>
Subject: Re: [PATCH] PREEMPT_RT_FULL: ARM context switch needs IRQs enabled

On Fri, Dec 16, 2011 at 08:56:29PM +0000, frank.rowand@...sony.com wrote:
> On 12/15/11 19:20, Frank Rowand wrote:
> > ARMv6 and later have VIPT caches and the TLBs are tagged with an ASID
> > (application specific ID). The number of ASIDs is limited to 256 and
> > the allocation algorithm requires IPIs when all the ASIDs have been
> > used.  The IPIs require interrupts enabled during context switch for
> > deadlock avoidance.
> > 
> > The RT patch mm-protect-activate-switch-mm.patch disables irqs around
> > activate_mm() and switch_mm(), which are the portion of the ARMv6
> > context switch that require interrupts enabled.
> > 
> > The solution for the ARMv6 processors could be to _not_ disable irqs.
> > A more conservative solution is to provide the same environment that
> > the scheduler provides, that is preempt_disable().  This is more
> > resilient for possible future changes to the ARM context switch code
> > that is not aware of the RT patches.
> > 
> > This patch will conflict slightly with Catalin's patch set to remove
> > __ARCH_WANT_INTERRUPTS_ON_CTXSW, when that is accepted:
> > 
> >    http://lkml.indiana.edu/hypermail/linux/kernel/1111.3/01893.html
> > 
> > When Catalin's patch set is accepted, this RT patch will need to reverse
> > the change in patch 6 to arch/arm/include/asm/system.h:
> > 
> >    -#ifndef CONFIG_CPU_HAS_ASID
> >    -#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
> >    -#endif
> > 
> > Signed-off-by: Frank Rowand <frank.rowand@...sony.com>
> > 
> > ---
> >  fs/exec.c        |    8 	8 +	0 -	0 !
> >  mm/mmu_context.c |    8 	8 +	0 -	0 !
> >  2 files changed, 16 insertions(+)
> > 
> > Index: b/fs/exec.c
> > ===================================================================
> > --- a/fs/exec.c
> > +++ b/fs/exec.c
> > @@ -837,12 +837,20 @@ static int exec_mmap(struct mm_struct *m
> >  		}
> >  	}
> >  	task_lock(tsk);
> > +#ifdef __ARCH_WANT_INTERRUPTS_ON_CTXSW
> 
> Self critique...  I really, really dislike this ifdef because it will
> fail silently if the includes are changed and as a result the include file that
> defines __ARCH_WANT_INTERRUPTS_ON_CTXSW (arch/arm/include/asm/system.h) is not
> included.
> 
> Does anyone have any brilliant ideas for an alternative approach?

What I don't like is reintroducing __ARCH_WANT_INTERRUPTS_ON_CTXSW as we
try to get rid of it. Can the -rt code not be modified to call
switch_mm() with interrupts enabled? The non-rt code seems to do this
anyway.

BTW, I pushed to fixups to the ctxsw changes for ARM:

http://git.kernel.org/?p=linux/kernel/git/cmarinas/linux.git;a=shortlog;h=refs/heads/intr-ctxsw

to cope with switch_mm() being called directly with interrupts enabled,
in which case it won't defer the pgd switch. I think I can improve them
a bit but it needs to wait until Monday (busy with Christmas shopping
this weekend).

-- 
Catalin
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ