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Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF177EE3A286@HQMAIL01.nvidia.com>
Date: Mon, 9 Jan 2012 13:30:05 -0800
From: Stephen Warren <swarren@...dia.com>
To: Peter De Schrijver <pdeschrijver@...dia.com>,
Peter De Schrijver <pdeschrijver@...dia.com>
CC: Colin Cross <ccross@...roid.com>, Olof Johansson <olof@...om.net>,
Russell King <linux@....linux.org.uk>,
"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [RESEND PATCH v2 0/3] Tegra30 clockframework
Peter De Schrijver wrote at Monday, January 09, 2012 8:35 AM:
> This patchset introduces the tegra30 clockframework. Clocks which require
> voltage scaling are not included in this version. The implementation doesn't
> use the generic clock code yet. It's the intention to move to it, once the
> semantics are fully clarified.
>
> ---
>
> Changes in v2:
> * Fix parent clocks for TWD. This makes the SMP configuration booting again.
Peter,
This version seems to still boot as well as without these patches.
I hacked some AUXDATA into board-dt-tegra30.c in an attempt to get SDHCI
working, but found that:
a) sdhci_add_host() fails due to:
mmc0: Hardware doesn't specify timeout clock frequency.
I haven't investigated why this happens.
b) More directly related to these patches, when sdhci_add_host() fails,
sdhci_tegra_probe() calls clk_disable() and clk_put() on its clock. One
of these hangs somehow. I assume that's a bug in this clock patch?
A couple of I2C devices did end up probing OK with these patches plus
AUXDATA, although I doubt any I2C accesses were actually performed.
--
nvpublic
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