linux-kernel - Re: Lapic vector priorites

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <alpine.LFD.2.00.1201230609560.22644@eddie.linux-mips.org>
Date:	Mon, 23 Jan 2012 06:24:09 +0000 (GMT)
From:	"Maciej W. Rozycki" <macro@...ux-mips.org>
To:	john stultz <johnstul@...ibm.com>
cc:	Thomas Gleixner <tglx@...utronix.de>,
	Clark Williams <williams@...hat.com>,
	Nivedita Singhvi <niv@...ibm.com>,
	lkml <linux-kernel@...r.kernel.org>, vosburgh@...ibm.com
Subject: Re: Lapic vector priorites

On Sun, 22 Jan 2012, john stultz wrote:

> I'm really not that familiar with the lapic code, but reading over some
> of the documentation I could find through searches, and then looking at
> the lapic vector layout in the kernel, I'm now a little curious.
> 
> >From what I've read the irq priority is set by the vector, where 0x0 is
> the highest and 0xFF is the lowest.
> 
> In irq_vectors.h I see:
> #define NMI_VECTOR			0x02
> #define MCE_VECTOR			0x12

 Both these vectors are hardwired internally in the CPU and irrelevant to 
the APIC interrupt priority levels as these apply to ordinary interrupts 
only.  For these the higher the vector value, the higher the priority (I 
won't get into the gory details, my memory has already faded about that 
and I'd have to resort to documentation to avoid confusion).

 The MCE is actually a processor exception and as such does not go through 
the APIC at all.  It's either signalled internally by the CPU (to record 
an internal malfunction) or via an external signal (to raise a bus error 
or a similar event).

 The NMI is the non-maskable interrupt and is driven by the local APIC on 
a separate processor's internal line (back in the 1990s where discrete 
local APICs were used this would actually be a separate board signal to 
the CPU) and it's the CPU that gives this line the priority above an 
ordinary interrupt that may be asserted at the same time.  For an NMI the 
CPU does not drive an INTA cycle (again, internally for modern processors) 
on its bus which the local APIC would respond with an interrupt vector to.

 I hope this helps.

  Maciej
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/