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Message-ID: <CABPqkBR2xBT-+sMw0+u3gTjpE1g+MgnghH+BBvi34XiXL+181g@mail.gmail.com>
Date: Mon, 6 Feb 2012 22:25:48 +0100
From: Stephane Eranian <eranian@...gle.com>
To: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc: Ingo Molnar <mingo@...e.hu>, Eric Dumazet <eric.dumazet@...il.com>,
Markus Trippelsdorf <markus@...ppelsdorf.de>,
linux-kernel@...r.kernel.org, Paul Mackerras <paulus@...ba.org>
Subject: Re: WARNING: at arch/x86/kernel/cpu/perf_event.c:989
On Mon, Feb 6, 2012 at 9:58 PM, Peter Zijlstra <a.p.zijlstra@...llo.nl> wrote:
> On Mon, 2012-02-06 at 21:44 +0100, Stephane Eranian wrote:
>> Which is pointing to the Intel specific:
>>
>> intel_pmu_handle_irq()
>> again:
>> intel_pmu_ack_status(status);
>> if (++loops > 100) {
>> WARN_ONCE(1, "perfevents: irq loop stuck!\n");
>> perf_event_print_debug();
>> intel_pmu_reset();
>> goto done;
>> }
>>
>> We are in a constant interrupt loop for a reason I don't yet understand.
>> Sure we have two counters going, bu given the callstack, one is being
>> stopped.
>>
>> I know we talked about that a couple of weeks back, but after all, it may
>> be that it is not possible to run the frequency adjustment code without
>> stopping the entire PMU because of risk of interrupts. But it is not clear
>> to me what's causing this at this point.
>
> There's Errata's on this, see AAK157 (SNB) BD106 (WSM) AAK157 (NHM).
>
Arg, I had forgotten about those.....
I'll check on this further with Intel.
> Ingo and I talked about a 'fix' for that based on the text in the SNB
> errata which explains why the reset works. Ingo I was under the
> impression you were going to implement that?
>
>> I suggest we still apply my patch to fix the x86_pmu_start() first, then
>> I will submit a second patch to fix that one. Agreed?
>
> Yes.
>
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