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Message-ID: <CAOtvUMfZ-sfTd-WTV=+RcerTk6ejC2mmjrMGg8KkdMR=RaV+CA@mail.gmail.com>
Date: Fri, 10 Feb 2012 22:13:23 +0200
From: Gilad Ben-Yossef <gilad@...yossef.com>
To: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc: Chris Metcalf <cmetcalf@...era.com>,
Frederic Weisbecker <fweisbec@...il.com>,
linux-kernel@...r.kernel.org, Christoph Lameter <cl@...ux.com>,
linux-mm@...ck.org, Pekka Enberg <penberg@...nel.org>,
Matt Mackall <mpm@...enic.com>,
Sasha Levin <levinsasha928@...il.com>,
Rik van Riel <riel@...hat.com>,
Andi Kleen <andi@...stfloor.org>, Mel Gorman <mel@....ul.ie>,
Andrew Morton <akpm@...ux-foundation.org>,
Alexander Viro <viro@...iv.linux.org.uk>,
Avi Kivity <avi@...hat.com>,
Michal Nazarewicz <mina86@...a86.com>,
Kosaki Motohiro <kosaki.motohiro@...il.com>,
Milton Miller <miltonm@....com>
Subject: Re: [v7 0/8] Reduce cross CPU IPI interference
On Fri, Feb 10, 2012 at 8:39 PM, Peter Zijlstra <a.p.zijlstra@...llo.nl> wrote:
> On Sun, 2012-02-05 at 13:46 +0200, Gilad Ben-Yossef wrote:
>> > /*
>> > * Cause all memory mappings to be populated in the page table.
>> > * Specifying this when entering dataplane mode ensures that no future
>> > * page fault events will occur to cause interrupts into the Linux
>> > * kernel, as long as no new mappings are installed by mmap(), etc.
>> > * Note that since the hardware TLB is of finite size, there will
>> > * still be the potential for TLB misses that the hypervisor handles,
>> > * either via its software TLB cache (fast path) or by walking the
>> > * kernel page tables (slow path), so touching large amounts of memory
>> > * will still incur hypervisor interrupt overhead.
>> > */
>> > #define DP_POPULATE 0x8
>>
>> hmm... I've probably missed something, but doesn't this replicate
>> mlockall (MCL_CURRENT|MCL_FUTURE) ?
>
> Never use mlockall() its a sign you're doing it wrong, also his comment
> seems to imply MCL_FUTURE isn't required.
>
My current understanding is that if I have a real time task and wish it
have a deterministic performance time, you should call mlockall() to lock
the program data and text into physical memory so that a less often taken
branch or access to a new data region will not result in a page fault.
You still have to worry about TLB misses on non hardware page table
walk architecture, but at least everything is in the page tables
If there is a better way to do this? I'm always happy to learn new
ways to do things. :-)
Thanks,
Gilad
--
Gilad Ben-Yossef
Chief Coffee Drinker
gilad@...yossef.com
Israel Cell: +972-52-8260388
US Cell: +1-973-8260388
http://benyossef.com
"If you take a class in large-scale robotics, can you end up in a
situation where the homework eats your dog?"
-- Jean-Baptiste Queru
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