lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20120213163711.GD3494@opensource.wolfsonmicro.com>
Date:	Mon, 13 Feb 2012 08:37:12 -0800
From:	Mark Brown <broonie@...nsource.wolfsonmicro.com>
To:	Laxman Dewangan <ldewangan@...dia.com>
Cc:	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: Regulator enable/disable delay based on board design: How to
 handle?

On Mon, Feb 13, 2012 at 02:48:18PM +0530, Laxman Dewangan wrote:

> We observed that some of the rail enable/disable settling time
> depends on the board design specially based on external capacitor
> connected on
> rails.  This is observed mainly on VBUS regulator rail where
> difference on the capacitance value which is connected on rail makes
> the on/off
> time to vary.

Usually this would be handled via regulator driver platform data as the
regulator will typically be designed with particular external components
in mind and (especially in the case of DCDC convertors) may need to be
configured differently depending on the choice of passive components.
Many regulators also have some software control for the ramp rate,
mainly intended to limit inrush currents on system startup, which can be
varied at runtime if desired.

Download attachment "signature.asc" of type "application/pgp-signature" (837 bytes)

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ