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Message-Id: <12BC8F06-26EE-4A58-8F0B-6D39C0DD7360@gmail.com>
Date:	Mon, 27 Feb 2012 11:10:55 -0500
From:	Ben Collins <benmcollins13@...il.com>
To:	Shengzhou Liu <Shengzhou.Liu@...escale.com>
Cc:	linux-kernel@...r.kernel.org
Subject: [Regression] powerpc/usb: fix issue of CPU halt when missing USB PHY clock

Hello,

The patch that checks the CTRL_PHY_CLK_VALID bit is failing incorrectly on my system (P4080DS). If I revert it, my system goes back to working correctly, but as is, it fails and wont allow my USB to work properly.

I've tried adding a loop to poll this bit 10,000 times with a udelay(1) on each loop and it still fails, so it doesn't appear to be a timing issue.

Is this check valid for all systems?

--
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My Blog   : http://ben-collins.blogspot.com/

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