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Message-Id: <20120228010206.714589800@linuxfoundation.org>
Date: Mon, 27 Feb 2012 17:02:19 -0800
From: Greg KH <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc: torvalds@...ux-foundation.org, akpm@...ux-foundation.org,
alan@...rguk.ukuu.org.uk, Nicolas Pitre <nico@...aro.org>,
Stephen Boyd <sboyd@...eaurora.org>,
Catalin Marinas <catalin.marinas@....com>,
Rabin Vincent <rabin@....in>,
Russell King <rmk+kernel@....linux.org.uk>
Subject: [ 16/73] ARM: 7325/1: fix v7 boot with lockdep enabled
3.0-stable review patch. If anyone has any objections, please let me know.
------------------
From: Rabin Vincent <rabin@....in>
commit 8e43a905dd574f54c5715d978318290ceafbe275 upstream.
Bootup with lockdep enabled has been broken on v7 since b46c0f74657d
("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR").
This is because v7_setup (which is called very early during boot) calls
v7_flush_dcache_all, and the save_and_disable_irqs added by that patch
ends up attempting to call into lockdep C code (trace_hardirqs_off())
when we are in no position to execute it (no stack, MMU off).
Fix this by using a notrace variant of save_and_disable_irqs. The code
already uses the notrace variant of restore_irqs.
Reviewed-by: Nicolas Pitre <nico@...aro.org>
Acked-by: Stephen Boyd <sboyd@...eaurora.org>
Cc: Catalin Marinas <catalin.marinas@....com>
Signed-off-by: Rabin Vincent <rabin@....in>
Signed-off-by: Russell King <rmk+kernel@....linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
arch/arm/include/asm/assembler.h | 5 +++++
arch/arm/mm/cache-v7.S | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -137,6 +137,11 @@
disable_irq
.endm
+ .macro save_and_disable_irqs_notrace, oldcpsr
+ mrs \oldcpsr, cpsr
+ disable_irq_notrace
+ .endm
+
/*
* Restore interrupt state previously stored in a register. We don't
* guarantee that this will preserve the flags.
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -55,7 +55,7 @@ loop1:
cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache
#ifdef CONFIG_PREEMPT
- save_and_disable_irqs r9 @ make cssr&csidr read atomic
+ save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
#endif
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr
--
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