linux-kernel - Re: [PATCH] Clear previous interrupts after fifo is disabled

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Message-ID: <20120228092140.GD18045@n2100.arm.linux.org.uk>
Date:	Tue, 28 Feb 2012 09:21:40 +0000
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	Chanho Min <chanho0207@...il.com>
Cc:	Alan Cox <alan@...ux.intel.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Shreshtha Kumar Sahu <shreshthakumar.sahu@...ricsson.com>,
	"Kim, Jong-Sung" <neidhard.kim@....com>,
	linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH] Clear previous interrupts after fifo is disabled

On Tue, Feb 28, 2012 at 06:16:10PM +0900, Chanho Min wrote:
> > RXFE _will_ be set.  Think about it - RXFE means Receive Fifo Empty.
> > If the receive fifo is empty, it _will_ be set.
> I know meaning of the RXFE. I also don't understand why RXFE is set by
> clearing FEN. We checked this by bellow debug codes.
> 
>  fr_before = readw(uap->port.membase + UART01x_FR);
>  writew(0, uap->port.membase + uap->lcrh_rx);
>  fr_after = readw(uap->port.membase + UART01x_FR);
> 
> If rx interrupt is ocurred before, fr_after becomes 0x90 but fr_before is 0x80.

Because the flags are manipulated to give the illusion of a one byte
FIFO, as stated in the TRM.

> > And RIS is the _Raw_ interrupt status.  That's the status _before_ the
> > mask is acted upon.
> >
> > But it won't be delivered because the mask register is zero.
> It can be delivered just after mask register is set to 1.

And we don't set the mask register to 1 until later.

> >> Root cause is that Rx interrupt set but Rx fifo is empty. If we just
> >> remove the sentence for clearing LCRH, nothing happens and interrupt
> >> handler don't this misbehave.
> >
> > No.
> When we just removed the sentence for clearing LCRH, this hangup doesn't
> happen.

But we want to do the transmit interrupt provocation with the FIFO disabled.
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