lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:	Tue, 28 Feb 2012 14:15:15 -0800
From:	Chris Wright <chrisw@...s-sol.org>
To:	"Mingarelli, Thomas" <Thomas.Mingarelli@...com>
Cc:	"dwmw2@...radead.org" <dwmw2@...radead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"ddutile@...hat.com" <ddutile@...hat.com>,
	Alex Williamson <alex.williamson@...hat.com>
Subject: Re: [Intel IOMMU PATCH] Re-evaluate RMRR info for devices removed
 from si domain

* Mingarelli, Thomas (Thomas.Mingarelli@...com) wrote:
> This patch is being submitted to handle the case where a pci device is
> placed into the si domain, when booting in iommu passthrough mode, then
> removed. The RMRR information for such devices need to be re-processed
> to avoid DMA Read errors due to the Present Bit being cleared in the
> device's context entry.

What happens if that device is attached to a VM, then detached and
rebound to a host driver?  I suspect the reserved memory range won't get
mapped properly for that device in that case.

thanks,
-chris
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ