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Message-ID: <4F5200BB.5090505@intel.com>
Date: Sat, 03 Mar 2012 19:30:03 +0800
From: Alex Shi <alex.shi@...el.com>
To: Ingo Molnar <mingo@...e.hu>
CC: tglx@...utronix.de, hpa@...or.com, mingo@...hat.com,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
x86@...nel.org, asit.k.mallick@...el.com
Subject: Re: change last level cache alignment on x86?
On 03/02/2012 11:25 PM, Ingo Molnar wrote:
> * Alex Shi <alex.shi@...el.com> wrote:
>
>> So, with defconfig on x86_64, I saw much changes in System.map:
>> before patched after patched
>> ...
>> 000000000000b000 d tlb_vector_| 000000000000b000 d tlb_vector
>> 000000000000b080 d cpu_loops_p| 000000000000b040 d cpu_loops_
>> ...
> Ok, mind sending a patch, changelogged, with a SOB?
Thanks a lot for review! A patch was sent to you.
> Thanks,
>
> Ingo
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