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Message-ID: <CACRpkdY3A_k_ywWgnFYG_3Jp+EssfULO0R59=GWUG2a0VS3--g@mail.gmail.com>
Date: Fri, 9 Mar 2012 17:34:03 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: Chanho Min <chanho0207@...il.com>,
Russell King <linux@....linux.org.uk>,
Alan Cox <alan@...ux.intel.com>,
Shreshtha Kumar Sahu <shreshthakumar.sahu@...ricsson.com>,
"Kim, Jong-Sung" <neidhard.kim@....com>,
linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH] Clear previous interrupts after fifo is disabled
On Thu, Mar 8, 2012 at 7:49 PM, Greg Kroah-Hartman
<gregkh@...uxfoundation.org> wrote:
> On Mon, Feb 27, 2012 at 06:30:20PM +0900, Chanho Min wrote:
>> This is another workaroud of 'https://lkml.org/lkml/2012/1/17/104'
>> with additional analysis.Bootloader can transfer control to kernel and
>> there are some pending interrupts. In this case, RXFE of the flag
>> register is set by clearing FEN(LCRH) even if rx data remains in the
>> fifo. It seems that the fifo's status is initiailized. Interrupt
>> handler can not get any data from data register because of the below
>> break condtion.
>>
>> pl011_fifo_to_tty
>> while (max_count--) {
>> if (status & UART01x_FR_RXFE)
>> break;
>
> This patch never seemed to be agreed on, so I'm not taking it.
>
> Can someone, if this is still needed, and everyone agrees on how to
> solve it, please send me the needed fix?
To me it seems Russell's patch solves part of the problem,
and Jong-Sung Kim's patch on top of that solves the entire
problem, but Chanho need to come back and tell whether
this is the case in practice.
Yours,
Linus Walleij
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