linux-kernel - Re: [PATCH 02/11 v3] drm/i915/intel_i2c: assign HDMI port D to pin pair 6

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Message-ID: <20120326150835.GQ4014@phenom.ffwll.local>
Date:	Mon, 26 Mar 2012 17:08:35 +0200
From:	Daniel Vetter <daniel@...ll.ch>
To:	Daniel Kurtz <djkurtz@...omium.org>,
	Keith Packard <keithp@...thp.com>,
	David Airlie <airlied@...ux.ie>,
	dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
	Chris Wilson <chris@...is-wilson.co.uk>,
	Benson Leung <bleung@...omium.org>,
	Yufeng Shen <miletus@...omium.org>
Subject: Re: [PATCH 02/11 v3] drm/i915/intel_i2c: assign HDMI port D to pin
 pair 6

On Mon, Mar 26, 2012 at 04:47:11PM +0200, Daniel Vetter wrote:
> On Mon, Mar 26, 2012 at 10:26:41PM +0800, Daniel Kurtz wrote:
> > According to i915 documentation [1], "Port D" (DP/HDMI Port D) is
> > actually gmbus pin pair 6 (gmbus0.2:0 == 110b GPIOF), not 7 (111b).
> > Pin pair 7 is a reserved pair.
> > 
> > [1] Documentation for [DevSNB+] and [DevIBX], as found on
> > http://intellinuxgraphics.org
> > 
> > Note: the "reserved" and "disabled" pairs do not actually map to a
> > physical pair of pins, nor GPIO regs and shouldn't be initialized or used.
> > Fixing this is left for a later patch.
> > 
> > This bug has not been noticed for two reasons:
> >  1) "gmbus" mode is currently disabled - all transfers are actually using
> >     "bit-bang" mode which uses the GPIO port 5 (the "HDMI/DPD CTLDATA/CLK"
> >     pair), at register 0x5024 (defined as GPIOF i915_reg.h).
> >     Since this is the correct pair of pins for HDMI1, transfers succeed.
> 
> ... this is no longer true on drm-intel-next.
> 
> >  2) Even if gmbus mode is re-enabled, the first attempted transaction
> >     will fail because it tries to use the wrong ("Reserved") pin pair.
> >     However, the driver immediately falls back again to the bit-bang
> >     method, which correctly uses GPIOF, so again, transfers succeed.
> > 
> > However, if gmbus mode is re-enabled and the GPIO fall-back mode is
> > disabled, then reading an attached monitor's EDID fail.
> > 
> > Signed-off-by: Daniel Kurtz <djkurtz@...omium.org>
> 
> Otherwise this looks ok to me - I've checked with gen3 Bspec and we seem
> to indeed have a 1:1 mapping, see "Display Registers", 1.5.3 "GPIO Control
> Registers", the list right below the heading.

well, scrap that, I've confused myself here a bit. Afaict we don't
actually use these gmbus ports on earlier chips.
> 
> Reviewed-by: Daniel Vetter <daniel.vetter@...ll.ch>
> 
> When resending, can you please add the Bspec reference above?

Can you you instead add a clear reference (Volume, Full Section plus
Heading Title) for the Snb/Ibx public Bspec.

Thanks, Daneil
-- 
Daniel Vetter
Mail: daniel@...ll.ch
Mobile: +41 (0)79 365 57 48
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