linux-kernel - [tip:perf/urgent] perf/x86: Add SNB offcore event constraints

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Message-ID: <tip-n6vf6grjv94vnzvuccu0clcv@git.kernel.org>
Date:	Tue, 27 Mar 2012 08:36:48 -0700
From:	tip-bot for Peter Zijlstra <a.p.zijlstra@...llo.nl>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, eranian@...gle.com, hpa@...or.com,
	mingo@...nel.org, a.p.zijlstra@...llo.nl, stable@...nel.org,
	tglx@...utronix.de
Subject: [tip:perf/urgent] perf/x86: Add SNB offcore event constraints

Commit-ID:  c370117c978adba861fad467427a9301c2c7082b
Gitweb:     http://git.kernel.org/tip/c370117c978adba861fad467427a9301c2c7082b
Author:     Peter Zijlstra <a.p.zijlstra@...llo.nl>
AuthorDate: Thu, 22 Mar 2012 11:41:23 +0100
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Tue, 27 Mar 2012 14:53:46 +0200

perf/x86: Add SNB offcore event constraints

As found in the Intel SDM (March 2012 edition) in Volume 3
section 18.8.5, the offcore response events are constrained
to PMC0 and PMC3 resp..

Signed-off-by: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc: Stephane Eranian <eranian@...gle.com>
Cc: <stable@...nel.org>
Link: http://lkml.kernel.org/n/tip-n6vf6grjv94vnzvuccu0clcv@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/perf_event_intel.c |   14 ++++++++------
 1 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 26b3e2f..bab8c6d 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -96,12 +96,14 @@ static struct event_constraint intel_westmere_event_constraints[] __read_mostly
 
 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 {
-	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
-	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
-	INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
-	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
-	INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
+	FIXED_EVENT_CONSTRAINT(0x00c0, 0),	/* INST_RETIRED.ANY */
+	FIXED_EVENT_CONSTRAINT(0x003c, 1),	/* CPU_CLK_UNHALTED.CORE */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2),	/* CPU_CLK_UNHALTED.REF */
+	INTEL_EVENT_CONSTRAINT(0x48, 0x4),	/* L1D_PEND_MISS.PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2),	/* INST_RETIRED.PREC_DIST */
+	INTEL_EVENT_CONSTRAINT(0xcd, 0x8),	/* MEM_TRANS_RETIRED.LOAD_LATENCY */
+	INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),	/* OFFCORE_RSP_0 */
+	INTEL_UEVENT_CONSTRAINT(0x01bb, 0x8),	/* OFFCORE_RSP_1 */
 	EVENT_CONSTRAINT_END
 };
 
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