linux-kernel - Re: [PATCH 2/7 v6] drm/i915/intel

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Message-ID: <1332960093_131068@CP5-2952>
Date:	Wed, 28 Mar 2012 19:41:21 +0100
From:	Chris Wilson <chris@...is-wilson.co.uk>
To:	Daniel Kurtz <djkurtz@...omium.org>,
	Daniel Vetter <daniel@...ll.ch>,
	Keith Packard <keithp@...thp.com>,
	David Airlie <airlied@...ux.ie>,
	dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Cc:	Benson Leung <bleung@...omium.org>,
	Yufeng Shen <miletus@...omium.org>,
	Daniel Kurtz <djkurtz@...omium.org>
Subject: Re: [PATCH 2/7 v6] drm/i915/intel_i2c: use double-buffered writes

On Thu, 29 Mar 2012 02:26:34 +0800, Daniel Kurtz <djkurtz@...omium.org> wrote:
> The GMBUS controller GMBUS3 register is double-buffered.  Take advantage
> of this  by writing two 4-byte words before the first wait for HW_RDY.
> This helps keep the GMBUS controller from becoming idle during long writes.
> 
> Signed-off-by: Daniel Kurtz <djkurtz@...omium.org>

"For byte counts that are greater than four bytes, this register will be
written with subsequent data only after the HW_RDY status bit is set"

Hmm, I had interpretted that as should only be. But if you take into
account that the register is indeed double-buffered, it does make sense
that the hardware itself is only updated after the HW_RDY signal.
Reviewed-by: Chris Wilson <chris@...is-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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