linux-kernel - Re: Blackfin link issue (Was: linux-next: triage for March 27, 2012)

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Message-ID: <CAMjpGUdJWxrHtaiAE-LQGZU7nNB1DSpiA9P78Rn5bB9+GyThjg@mail.gmail.com>
Date:	Tue, 27 Mar 2012 23:34:39 -0400
From:	Mike Frysinger <vapier@...too.org>
To:	Stephen Rothwell <sfr@...b.auug.org.au>
Cc:	Paul Gortmaker <paul.gortmaker@...driver.com>,
	linux-next@...r.kernel.org, linux-kernel@...r.kernel.org,
	Bob Liu <lliubbo@...il.com>,
	uclinux-dist-devel@...ckfin.uclinux.org
Subject: Re: Blackfin link issue (Was: linux-next: triage for March 27, 2012)

On Tue, Mar 27, 2012 at 20:03, Stephen Rothwell wrote:
> On Tue, 27 Mar 2012 17:36:27 -0400 Paul Gortmaker wrote:
>> The blackfin builds are no longer failing on vm_is_stack but instead
>> are all failing with "L1 data A overflow!" at final link, which smells
>> like some kind of binutils/toolchain issue.
>>
>>
>> bfin:***all-builds***
>>       when:   Mar 26
>>       why:    bfin-uclinux-ld: L1 data A overflow!
>>       status: unknown, binutils issue?
>>       fix:
>>       ref:    http://kisskb.ellerman.id.au/kisskb/buildresult/5981475/
>
> It actually looks like this comes from an ASSERT in the blackfin
> vmlinux.lds.S ... looks like some sections overflowed.

yes, the assert is doing the right thing.  it's attempting to put
24KiB into a region that can only hold 16KiB.

this is due to the recent lib/gen_crc32table.c change:
  46c5801eaf86e83cb3a4142ad35188db5011fff0
  crc32: bolt on crc32c

it added 8KiB more data.  looks to me like it's a complete waste of
space ... it's forced into __cacheline_aligned which doesn't let the
linker do garbage collection on symbols/sections, so all systems are
forced to carry this.  seems like this should be a Kconfig knob that
other people would select if they actually need it ?

at any rate, would be easy to fix by disabling Kconfig
CACHELINE_ALIGNED_L1 when CRC32 is enabled considering that makes the
optimization completely useless by totally blowing the size out of the
water.

--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -823,7 +823,7 @@
    bool "Locate cacheline_aligned data to L1 Data Memory"
    default y if !BF54x
    default n if BF54x
-   depends on !SMP && !BF531
+   depends on !SMP && !BF531 && !CRC32
    help
      If enabled, cacheline_aligned data is linked
      into L1 data memory. (less latency)
-mike
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