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Message-ID: <CAGS+omBWDoc2YiKPmBJ7=iEr+1DFBZp0EDCpPwP9c7FcbC4iew@mail.gmail.com> Date: Thu, 29 Mar 2012 16:37:18 +0800 From: Daniel Kurtz <djkurtz@...omium.org> To: Chris Wilson <chris@...is-wilson.co.uk> Cc: Daniel Vetter <daniel@...ll.ch>, Keith Packard <keithp@...thp.com>, David Airlie <airlied@...ux.ie>, dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org, Benson Leung <bleung@...omium.org>, Yufeng Shen <miletus@...omium.org> Subject: Re: [PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions On Thu, Mar 29, 2012 at 2:52 AM, Chris Wilson <chris@...is-wilson.co.uk> wrote: > On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz <djkurtz@...omium.org> wrote: >> It is very common for an i2c device to require a small 1 or 2 byte write >> followed by a read. For example, when reading from an i2c EEPROM it is >> common to write and address, offset or index followed by a reading some >> values. > > Hmm, I have > > "gmbus1, bits 8-15: 8-bit GMBUS slave register > This field is redundant and should not be used." > > Scary. :) Perhaps INDEX ops are only available on some chipsets? Is this something you can double check? > > Otherwise, the code itself looks correct and quite neatly done now. > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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