linux-kernel - RE: [PATCH v2] i2c: tegra: Add delay before reset the controller

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Date:	Mon, 2 Apr 2012 17:36:45 +0530
From:	Alok Chauhan <alokc@...dia.com>
To:	Shubhrajyoti Datta <omaplinuxkernel@...il.com>
CC:	Stephen Warren <swarren@...dotorg.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"khali@...ux-fr.org" <khali@...ux-fr.org>,
	"ben-linux@...ff.org" <ben-linux@...ff.org>,
	"w.sang@...gutronix.de" <w.sang@...gutronix.de>,
	Stephen Warren <swarren@...dia.com>,
	"olof@...om.net" <olof@...om.net>,
	"bones@...retlab.ca" <bones@...retlab.ca>,
	"ccross@...roid.com" <ccross@...roid.com>,
	Laxman Dewangan <ldewangan@...dia.com>,
	"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
	"linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>,
	"dgreid@...omium.org" <dgreid@...omium.org>
Subject: RE: [PATCH v2] i2c: tegra: Add delay before reset the controller

Hi Shubhrajyoti,

> Why is it clock cycle dependent?
I think you got me wrong. What I meant to say that delay is calculated based on clock period of that bus. So in this way I don't have to hardcode the delay value.

> Is it possible to poll if the stop is sent by controller ?
No, Tegra i2c controller doesn't have any register for STOP condition completion status bit. So delay is the only option here.

Thanks
Alok

-----Original Message-----
From: Shubhrajyoti Datta [mailto:omaplinuxkernel@...il.com] 
Sent: Monday, April 02, 2012 3:49 PM
To: Alok Chauhan
Cc: Stephen Warren; linux-kernel@...r.kernel.org; khali@...ux-fr.org; ben-linux@...ff.org; w.sang@...gutronix.de; Stephen Warren; olof@...om.net; bones@...retlab.ca; ccross@...roid.com; Laxman Dewangan; linux-tegra@...r.kernel.org; linux-i2c@...r.kernel.org; dgreid@...omium.org
Subject: Re: [PATCH v2] i2c: tegra: Add delay before reset the controller

Hi Alok,
Few / doubts /questions.


On Mon, Apr 2, 2012 at 11:29 AM, Alok Chauhan <alokc@...dia.com> wrote:
> Stephen,
>
> I've updated the commit message and comment in the code as per your suggestion. Tegra I2C controller doesn't have idle bit so delay is required before reset the controller in case of NACK error.  This delay is calculated purely based on clock period of that particular i2c bus and not passed as hardcoded value. I2C SCL clock-stretching won't affect this calculated delay.

Why is it clock cycle dependent?

Is it possible to poll if the stop is sent by controller ?

>
> Thanks
> Alok
>
>
> -----Original Message-----
> From: Alok Chauhan [mailto:alokc@...dia.com]
> Sent: Monday, April 02, 2012 11:23 AM
> To: swarren@...dotorg.org; khali@...ux-fr.org; ben-linux@...ff.org; w.sang@...gutronix.de; Stephen Warren; olof@...om.net; bones@...retlab.ca; omaplinuxkernel@...il.com; ccross@...roid.com; Laxman Dewangan; linux-tegra@...r.kernel.org; linux-i2c@...r.kernel.org; dgreid@...omium.org
> Cc: Alok Chauhan; linux-kernel@...r.kernel.org
> Subject: [PATCH v2] i2c: tegra: Add delay before reset the controller
>
> NACK interrupt generated before I2C controller generates the STOP condition on bus. In Software, because of this reset of controller is happening before I2C controller could complete STOP condition. So wait for some time before resetting the controller so that STOP condition has delivered properly on bus.
>
> Added delay of 2 clock period
How did you calculate the 2 clock cycles?


before reset the controller in case of NACK error.
>
> Signed-off-by: Alok Chauhan <alokc@...dia.com>
> ---
> Added the more descriptive commit message about issue in case of NACK error condition. Changed the comment in code also
>
>  drivers/i2c/busses/i2c-tegra.c |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
>
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