linux-kernel - Re: [PATCH-v3] Support M95040 SPI EEPROM

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Tue, 3 Apr 2012 09:53:20 -0700
From:	Chris Wright <chrisw@...s-sol.org>
To:	Ivo Sieben <meltedpianoman@...il.com>
Cc:	linux-kernel@...r.kernel.org, Wolfram Sang <w.sang@...gutronix.de>,
	Jean Delvare <khali@...ux-fr.org>,
	Kevin Hilman <khilman@...prootsystems.com>,
	Chris Wright <chrisw@...s-sol.org>
Subject: Re: [PATCH-v3] Support M95040 SPI EEPROM

* Ivo Sieben (meltedpianoman@...il.com) wrote:
> +	instr = AT25_READ;
> +	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
> +		if (offset >= (1U << (at25->addrlen * 8)))
> +			instr |= AT25_INSTR_BIT3;
> +	*cp++ = instr;
<snip>
> +	/*
> +	 * Certain EEPROMS have a size that is larger than the number of address
> +	 * bytes would allow (e.g. like M95040 from ST that has 512 Byte size
> +	 * but uses only one address byte (A0 to A7) for addressing.) For
> +	 * the extra address bit (A8, A16 or A24) bit 3 of the instruction byte
> +	 * is used. This instruction bit is normally defined as don't care for
> +	 * other AT25 like chips.
> +	 */
> +#define EE_INSTR_BIT3_IS_ADDR	0x0010

Is there some guarantee that this chip flag will always have this
meaning?

thanks,
-chris
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/