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Message-Id: <201204091324.34288.arnd@arndb.de> Date: Mon, 9 Apr 2012 13:24:33 +0000 From: Arnd Bergmann <arnd@...db.de> To: Chris Metcalf <cmetcalf@...era.com> Cc: linux-kernel@...r.kernel.org Subject: Re: [PATCH 3/6] arch/tile: support MMIO-based readb/writeb etc. On Friday 06 April 2012, Chris Metcalf wrote: > Add support for MMIO read/write on tilegx to support GXIO IORPC access. > Similar to the asm-generic version, but we include memory fences on > the writes to be conservative. > > Signed-off-by: Chris Metcalf <cmetcalf@...era.com> It's usually better to use inline assembly here, to guarantee that the compiler does not split an access into multiple byte sized accesses as it might sometimes do if a register data structure is marged "packed". The "volatile" guarantees that the access does not go beyond a single word, but it does not guarantee that it's atomic. I don't think you need the fences after the write because PCI MMIO writes are posted anyway (only PIO is non-posted), but you might need some kind of barrier on the read to prevent a scenario where an MMIO read tells you that a DMA has completed, but the CPU (or the compiler) has scheduled the read of that data ahead of the MMIO read. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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