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Message-ID: <20120409101119.47e770b2@jbarnes-desktop>
Date: Mon, 9 Apr 2012 10:11:19 -0700
From: Jesse Barnes <jbarnes@...tuousgeek.org>
To: Chris Wilson <chris@...is-wilson.co.uk>
Cc: Jiri Slaby <jslaby@...e.cz>, Jiri Slaby <jirislaby@...il.com>,
LKML <linux-kernel@...r.kernel.org>,
dri-devel@...ts.freedesktop.org
Subject: Re: i915_driver_irq_handler: irq 42: nobody cared
On Fri, 30 Mar 2012 11:45:43 +0100
Chris Wilson <chris@...is-wilson.co.uk> wrote:
> On Fri, 30 Mar 2012 11:59:28 +0200, Jiri Slaby <jslaby@...e.cz> wrote:
> > I don't know what to dump more, because iir is obviously zero too. What
> > other sources of interrupts are on the (G33) chip?
>
> IIR is the master interrupt, with chained secondary interrupt statuses.
> If IIR is 0, the interrupt wasn't raised by the GPU.
I've actually seen cases where one of the PIPE*STAT regs is stuck, and
even if IIR is 0 we still get interrupts... Jiri can you verify the
PIPE*STAT regs have bits set, maybe one or more we don't check for?
--
Jesse Barnes, Intel Open Source Technology Center
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