lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Wed, 11 Apr 2012 18:29:39 +0200
From:	Joerg Roedel <joerg.roedel@....com>
To:	Greg KH <gregkh@...uxfoundation.org>
CC:	<linux-kernel@...r.kernel.org>, <stable@...r.kernel.org>
Subject: Re: [PATCH 3.2-stable] iommu/amd: Make sure IOMMU interrupts are
 re-enabled on resume

On Wed, Apr 11, 2012 at 06:25:46PM +0200, Joerg Roedel wrote:
> commit 9ddd592a191b32f2ee6c4b6ed2bd52665c3a49f5 upstream
> 
> Unfortunatly the interrupts for the event log and the
> peripheral page-faults are only enabled at boot but not
> re-enabled at resume. Fix that for 3.2.
> 
> Cc: stable@...r.kernel.org
> Signed-off-by: Joerg Roedel <joerg.roedel@....com>

Argh, please ignore this one, this patch does a little bit too much.

> ---
>  drivers/iommu/amd_iommu_init.c |   27 ++++++++++++++++++++-------
>  1 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
> index 5c74179..c90a709 100644
> --- a/drivers/iommu/amd_iommu_init.c
> +++ b/drivers/iommu/amd_iommu_init.c
> @@ -1033,8 +1033,9 @@ static int iommu_setup_msi(struct amd_iommu *iommu)
>  {
>  	int r;
>  
> -	if (pci_enable_msi(iommu->dev))
> -		return 1;
> +	r = pci_enable_msi(iommu->dev);
> +	if (r)
> +		return r;
>  
>  	r = request_threaded_irq(iommu->dev->irq,
>  				 amd_iommu_int_handler,
> @@ -1044,24 +1045,36 @@ static int iommu_setup_msi(struct amd_iommu *iommu)
>  
>  	if (r) {
>  		pci_disable_msi(iommu->dev);
> -		return 1;
> +		return r;
>  	}
>  
>  	iommu->int_enabled = true;
> -	iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
>  
>  	return 0;
>  }
>  
>  static int iommu_init_msi(struct amd_iommu *iommu)
>  {
> +	int ret;
> +
>  	if (iommu->int_enabled)
> -		return 0;
> +		goto enable_faults;
>  
>  	if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
> -		return iommu_setup_msi(iommu);
> +		ret = iommu_setup_msi(iommu);
> +	else
> +		ret = -ENODEV;
>  
> -	return 1;
> +	if (ret)
> +		return ret;
> +
> +enable_faults:
> +	iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
> +
> +	if (iommu->ppr_log != NULL)
> +		iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
> +
> +	return 0;
>  }
>  
>  /****************************************************************************
> -- 
> 1.7.5.4

-- 
AMD Operating System Research Center

Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ