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Message-ID: <20120418071040.GB31135@sequoia.sous-sol.org>
Date: Wed, 18 Apr 2012 00:10:40 -0700
From: Chris Wright <chrisw@...s-sol.org>
To: Ivo Sieben <meltedpianoman@...il.com>
Cc: Greg KH <gregkh@...uxfoundation.org>,
Remy Bohmer <linux@...mer.net>,
Chris Wright <chrisw@...s-sol.org>,
linux-kernel@...r.kernel.org, Jean Delvare <khali@...ux-fr.org>,
Kevin Hilman <khilman@...prootsystems.com>,
Wolfram Sang <w.sang@...gutronix.de>
Subject: Re: [PATCH-v4] Support M95040 SPI EEPROM
* Ivo Sieben (meltedpianoman@...il.com) wrote:
> Updated the generic SPI EEPROM driver AT25 for support of an additional address
> bit in the instruction byte. Certain EEPROMS have a size that is larger than the
> number of address bytes would allow (e.g. like M95040 from ST that has 512 Byte
> size but uses only one address byte (A0 to A7) for addressing.) For the extra
> address bit (A8, A16 or A24) bit 3 of the instruction byte is used. This
> instruction bit is normally defined as don't care for other AT25 like chips.
>
> Reviewed-by: Wolfram Sang <w.sang@...gutronix.de>
> Signed-off-by: Ivo Sieben <meltedpianoman@...il.com>
Acked-by: Chris Wright <chrisw@...s-sol.org>
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