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Message-ID: <3908561D78D1C84285E8C5FCA982C28F170F319D@ORSMSX104.amr.corp.intel.com> Date: Tue, 24 Apr 2012 17:31:12 +0000 From: "Luck, Tony" <tony.luck@...el.com> To: Borislav Petkov <bp@...64.org>, Mauro Carvalho Chehab <mchehab@...hat.com> CC: Linux Edac Mailing List <linux-edac@...r.kernel.org>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, Doug Thompson <norsk5@...oo.com> Subject: RE: [EDAC PATCH v13 6/7] edac.h: Prepare to handle with generic layers > @Tony: hey Tony, can you point us to an Intel document explaining how > Sandy Bridge or NH or one of the new ones does the memory addressing wrt > ranks, channels etc? Thanks. Data sheets for the E5-26xx series (vol 1 & 2) are linked off this page: http://www.intel.com/content/www/us/en/processors/xeon/xeon-processor-5000-sequence/Xeon5000TechnicalResources.html volume 2, section 4.4 is where this stuff is described ... BUT I'm not sure if everything needed made it into them from the internal docs (which we let Mauro use to write the sb_edac.c driver and then got a special exemption to let him post the driver before the public docs existed ... which means there *might* be some things that are only publicly documented in the EDAC driver). -Tony -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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