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Message-ID: <20120425093001.GA18882@aftab.osrc.amd.com>
Date:	Wed, 25 Apr 2012 11:30:01 +0200
From:	Borislav Petkov <borislav.petkov@....com>
To:	Ingo Molnar <mingo@...hat.com>, "H. Peter Anvin" <hpa@...or.com>
CC:	<x86@...nel.org>, <kernel-janitors@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>,
	"Srivatsa S. Bhat" <srivatsa.bhat@...ux.vnet.ibm.com>,
	Frank Arnold <frank.arnold@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Dan Carpenter <dan.carpenter@...cle.com>
Subject: Re: [GIT PULL] L3 CID fix for 3.5

Ping?

Guys, any issues with this that I should know of?

Thanks.

On Thu, Apr 19, 2012 at 06:53:53PM +0200, Borislav Petkov wrote:
> Hi guys,
> 
> please pull the following fix for L3 cache index disable into tip. Since
> there's no real breakage but simply a correctness issue, it can wait for
> 3.5. I've also removed the stable tag I had in the previous version.
> 
> Thanks.
> 
> --
> The following changes since commit e816b57a337ea3b755de72bec38c10c864f23015:
> 
>   Linux 3.4-rc3 (2012-04-15 18:28:29 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git tags/l3-fix-for-3.5
> 
> for you to fetch changes up to a720b2dd2470a52345df11dca8d6c1466599f812:
> 
>   x86, intel_cacheinfo: Fix error return code in amd_set_l3_disable_slot() (2012-04-19 18:30:28 +0200)
> 
> ----------------------------------------------------------------
> A small L3 cache index disable fix from Srivatsa Bhat which unifies the
> way the code checks for already disabled indices.
> 
> ----------------------------------------------------------------
> Srivatsa S. Bhat (1):
>       x86, intel_cacheinfo: Fix error return code in amd_set_l3_disable_slot()
> 
>  arch/x86/kernel/cpu/intel_cacheinfo.c |    8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> Appending patch here too:
> 
> --
> commit a720b2dd2470a52345df11dca8d6c1466599f812
> Author: Srivatsa S. Bhat <srivatsa.bhat@...ux.vnet.ibm.com>
> Date:   Thu Apr 19 12:35:08 2012 +0200
> 
>     x86, intel_cacheinfo: Fix error return code in amd_set_l3_disable_slot()
>     
>     If the L3 disable slot is already in use, return -EEXIST instead of
>     -EINVAL. The caller, store_cache_disable(), checks this return value to
>     print an appropriate warning.
>     
>     Also, we want to signal with -EEXIST that the current index we're
>     disabling has actually been already disabled on the node:
>     
>     $ echo 12 > /sys/devices/system/cpu/cpu3/cache/index3/cache_disable_0
>     $ echo 12 > /sys/devices/system/cpu/cpu3/cache/index3/cache_disable_0
>     -bash: echo: write error: File exists
>     $ echo 12 > /sys/devices/system/cpu/cpu3/cache/index3/cache_disable_1
>     -bash: echo: write error: File exists
>     $ echo 12 > /sys/devices/system/cpu/cpu5/cache/index3/cache_disable_1
>     -bash: echo: write error: File exists
>     
>     The old code would say
>     
>     -bash: echo: write error: Invalid argument
>     
>     for disable slot 1 when playing the example above with no output in
>     dmesg, which is clearly misleading.
>     
>     Reported-by: Dan Carpenter <dan.carpenter@...cle.com>
>     Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@...ux.vnet.ibm.com>
>     Link: http://lkml.kernel.org/r/20120419070053.GB16645@elgon.mountain
>     [Boris: add testing for the other index too]
>     Signed-off-by: Borislav Petkov <borislav.petkov@....com>
> 
> diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
> index 73d08ed98a64..b8f3653dddbc 100644
> --- a/arch/x86/kernel/cpu/intel_cacheinfo.c
> +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
> @@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot,
>  	/*  check if @slot is already used or the index is already disabled */
>  	ret = amd_get_l3_disable_slot(nb, slot);
>  	if (ret >= 0)
> -		return -EINVAL;
> +		return -EEXIST;
>  
>  	if (index > nb->l3_cache.indices)
>  		return -EINVAL;
>  
>  	/* check whether the other slot has disabled the same index already */
>  	if (index == amd_get_l3_disable_slot(nb, !slot))
> -		return -EINVAL;
> +		return -EEXIST;
>  
>  	amd_l3_disable_index(nb, cpu, slot, index);
>  
> @@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
>  	err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val);
>  	if (err) {
>  		if (err == -EEXIST)
> -			printk(KERN_WARNING "L3 disable slot %d in use!\n",
> -					    slot);
> +			pr_warning("L3 slot %d in use/index already disabled!\n",
> +				   slot);
>  		return err;
>  	}
>  	return count;
> 
> -- 
> Regards/Gruss,
> Boris.
> 
> Advanced Micro Devices GmbH
> Einsteinring 24, 85609 Dornach
> GM: Alberto Bozzo
> Reg: Dornach, Landkreis Muenchen
> HRB Nr. 43632 WEEE Registernr: 129 19551
> _______________________________________________
> osrc-patches mailing list
> osrc-patches@...e.amd.com
> https://elbe.amd.com/mailman/listinfo/osrc-patches

-- 
Regards/Gruss,
Boris.

Advanced Micro Devices GmbH
Einsteinring 24, 85609 Dornach
GM: Alberto Bozzo
Reg: Dornach, Landkreis Muenchen
HRB Nr. 43632 WEEE Registernr: 129 19551

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