linux-kernel - [tip:x86/cpu] x86/cache_info: Fix setup of l2/l3 ids

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Message-ID: <tip-ddc5681ed33a279fdc188e98e71f0c539f08c6e6@git.kernel.org>
Date:	Mon, 7 May 2012 21:24:06 -0700
From:	tip-bot for Shai Fultheim <shai@...lemp.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...nel.org,
	travis@....com, andreas.herrmann3@....com, davej@...hat.com,
	shai@...lemp.com, tglx@...utronix.de, ido@...ery.com,
	borislav.petkov@....com
Subject: [tip:x86/cpu] x86/cache_info: Fix setup of l2/l3 ids

Commit-ID:  ddc5681ed33a279fdc188e98e71f0c539f08c6e6
Gitweb:     http://git.kernel.org/tip/ddc5681ed33a279fdc188e98e71f0c539f08c6e6
Author:     Shai Fultheim <shai@...lemp.com>
AuthorDate: Fri, 20 Apr 2012 01:09:11 +0300
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Mon, 7 May 2012 15:27:37 +0200

x86/cache_info: Fix setup of l2/l3 ids

On some architectures (such as vSMP), it is possible to have
CPUs with a different number of cores sharing the same cache.

The current implementation implicitly assumes that all CPUs will
have the same number of cores sharing caches, and as a result,
different CPUs can end up with the same l2/l3 ids.

Fix this by masking out the shared cache bits, instead of
shifting the APICID. By doing so, it is guaranteed that the
generated cache ids are always unique.

Signed-off-by: Shai Fultheim <shai@...lemp.com>
[ rebased, simplified, and reworded the commit message]
Signed-off-by: Ido Yariv <ido@...ery.com>
Cc: Borislav Petkov <borislav.petkov@....com>
Cc: Andreas Herrmann <andreas.herrmann3@....com>
Cc: Mike Travis <travis@....com>
Cc: Dave Jones <davej@...hat.com>
Link: http://lkml.kernel.org/r/1334873351-31142-1-git-send-email-ido@wizery.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index b8f3653..9a7c90d 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -615,14 +615,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
 					new_l2 = this_leaf.size/1024;
 					num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
 					index_msb = get_count_order(num_threads_sharing);
-					l2_id = c->apicid >> index_msb;
+					l2_id = c->apicid & ~((1 << index_msb) - 1);
 					break;
 				case 3:
 					new_l3 = this_leaf.size/1024;
 					num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
 					index_msb = get_count_order(
 							num_threads_sharing);
-					l3_id = c->apicid >> index_msb;
+					l3_id = c->apicid & ~((1 << index_msb) - 1);
 					break;
 				default:
 					break;
--
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