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Message-Id: <20120510173133.584262248@linuxfoundation.org>
Date: Thu, 10 May 2012 10:31:39 -0700
From: Greg KH <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc: torvalds@...ux-foundation.org, akpm@...ux-foundation.org,
alan@...rguk.ukuu.org.uk, Dave Airlie <airlied@...hat.com>,
Kenneth Graunke <kenneth@...tecape.org>,
Daniel Vetter <daniel.vetter@...ll.ch>
Subject: [ 07/52] drm/i915: Do no set Stencil Cache eviction LRA w/a on gen7+
3.3-stable review patch. If anyone has any objections, please let me know.
------------------
From: Daniel Vetter <daniel.vetter@...ll.ch>
commit 2e7a44814d802c8ba479164b8924070cd908d6b5 upstream.
I've flagged this while reviewing the first version and Ken Graunke
fixed it up in v2, but unfortunately Dave Airlie picked up the wrong
version.
Cc: Dave Airlie <airlied@...hat.com>
Cc: Kenneth Graunke <kenneth@...tecape.org>
Signed-Off-by: Daniel Vetter <daniel.vetter@...ll.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -414,10 +414,8 @@ static int init_render_ring(struct intel
return ret;
}
- if (INTEL_INFO(dev)->gen >= 6) {
- I915_WRITE(INSTPM,
- INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
+ if (IS_GEN6(dev)) {
/* From the Sandybridge PRM, volume 1 part 3, page 24:
* "If this bit is set, STCunit will have LRA as replacement
* policy. [...] This bit must be reset. LRA replacement
@@ -427,6 +425,11 @@ static int init_render_ring(struct intel
CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
}
+ if (INTEL_INFO(dev)->gen >= 6) {
+ I915_WRITE(INSTPM,
+ INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
+ }
+
return ret;
}
--
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