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Message-ID: <20120513100532.GC28863@aftab.osrc.amd.com>
Date: Sun, 13 May 2012 12:05:32 +0200
From: Borislav Petkov <bp@...64.org>
To: "Luck, Tony" <tony.luck@...el.com>
Cc: Chen Gong <gong.chen@...ux.intel.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Ingo Molnar <mingo@...e.hu>,
"Huang, Ying" <ying.huang@...el.com>,
Hidetoshi Seto <seto.hidetoshi@...fujitsu.com>
Subject: Re: [PATCH 2/2] x86/mce: Add instruction recovery signatures to
mce-severity table
On Fri, May 11, 2012 at 05:42:09PM +0000, Luck, Tony wrote:
> > For IFU, on affected logical processors, RIPV and EIPV both are 0,
> > since now new IFU entries are added into severity table, the old
> > entry as below should be removed:
> >
> > /* Neither return not error IP -- no chance to recover -> PANIC */
> > MCESEV(
> > PANIC, "Neither restart nor error IP",
> > MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
> > ),
>
> We need to keep this. If EIPV is not set, then CS and IP on the
> stack are not guaranteed ... so we can't tell whether the error
> happened in user or kernel mode. This makes recovery "challenging".
>
> I'm trying to figure out a quirk for processors that do generate
> EIPV=RIPV=0 signature for IFU errors. There are some case where
> we can work around the lack of EIPV.
__mcheck_cpu_apply_quirks?
--
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Advanced Micro Devices GmbH
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