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Message-ID: <20120515140457.GB27806@aftab.osrc.amd.com>
Date: Tue, 15 May 2012 16:04:57 +0200
From: Borislav Petkov <bp@...64.org>
To: Steven Rostedt <rostedt@...dmis.org>
Cc: Peter Zijlstra <a.p.zijlstra@...llo.nl>,
Luming Yu <luming.yu@...il.com>,
Nick Piggin <npiggin@...il.com>, Alex Shi <alex.shi@...el.com>,
tglx@...utronix.de, mingo@...hat.com, hpa@...or.com, arnd@...db.de,
fweisbec@...il.com, jeremy@...p.org, riel@...hat.com, luto@....edu,
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cpw@....com, steiner@....com, akpm@...ux-foundation.org,
penberg@...nel.org, hughd@...gle.com, rientjes@...gle.com,
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Subject: Re: [PATCH v5 6/7] x86/tlb: optimizing flush_tlb_mm
On Tue, May 15, 2012 at 09:39:05AM -0400, Steven Rostedt wrote:
> > But you have to weight that against the cost of re-population, and
> > that's the difficult bit, since we have no clue how many tlb entries are
> > in use by the current cr3.
> >
> > It might be possible for intel to give us this information, I've asked
> > for something similar for cachelines.
>
> What information? The # of tlb entries in use?
... by the current %cr3, yes.
And also, before we delve into details, we still don't have a
representative benchmark where this shows any improvement.
--
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