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Message-ID: <CAPM=9tyZLm+F1Sq3-ycOS7GmedjiU7DR-GQ=4Hj0BzaAxHHYxQ@mail.gmail.com>
Date: Wed, 23 May 2012 08:21:51 +0100
From: Dave Airlie <airlied@...il.com>
To: Yinghai Lu <yinghai@...nel.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Linus Torvalds <torvalds@...ux-foundation.org>,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>
Subject: Re: [PATCH 03/11] intel-gtt: Read 64bit for gmar_bus_addr
On Wed, May 23, 2012 at 7:34 AM, Yinghai Lu <yinghai@...nel.org> wrote:
> That bar could be 64bit pref mem.
>
> Signed-off-by: Yinghai Lu <yinghai@...nel.org>
> Cc: David Airlie <airlied@...ux.ie>
Adding Daniel Vetter.
Dave.
> ---
> drivers/char/agp/intel-gtt.c | 14 ++++++++++----
> 1 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 7f025fb..77e150e 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -770,16 +770,22 @@ static void i830_write_entry(dma_addr_t addr, unsigned int entry,
> static bool intel_enable_gtt(void)
> {
> u32 gma_addr;
> + u32 addr_hi = 0;
> u8 __iomem *reg;
> + int pos;
>
> if (INTEL_GTT_GEN <= 2)
> - pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
> - &gma_addr);
> + pos = I810_GMADDR;
> else
> - pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
> - &gma_addr);
> + pos = I915_GMADDR;
> +
> + pci_read_config_dword(intel_private.pcidev, pos, &gma_addr);
> +
> + if (gma_addr & PCI_BASE_ADDRESS_MEM_TYPE_64)
> + pci_read_config_dword(intel_private.pcidev, pos + 4, &addr_hi);
>
> intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
> + intel_private.gma_bus_addr |= (u64)addr_hi << 32;
>
> if (INTEL_GTT_GEN >= 6)
> return true;
> --
> 1.7.7
>
> --
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