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Message-ID: <CABPqkBQYrZ9V3avxhJ1Qid=QKkbYcpc0cTeJXE8wJyVOoEZuaQ@mail.gmail.com>
Date: Thu, 24 May 2012 11:06:33 +0200
From: Stephane Eranian <eranian@...gle.com>
To: Namhyung Kim <namhyung.kim@....com>
Cc: Peter Zijlstra <a.p.zijlstra@...llo.nl>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
Paul Mackerras <paulus@...ba.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] perf, x86: Make cycles:p working on SNB
On Thu, May 24, 2012 at 10:59 AM, Namhyung Kim <namhyung.kim@....com> wrote:
> Hi, Stephane
>
> On Thu, 24 May 2012 09:41:45 +0200, Stephane Eranian wrote:
>> On Thu, May 24, 2012 at 9:27 AM, Peter Zijlstra <a.p.zijlstra@...llo.nl> wrote:
>>> On Thu, 2012-05-24 at 12:02 +0900, Namhyung Kim wrote:
>>>
>>>> --- a/arch/x86/kernel/cpu/perf_event_intel.c
>>>> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
>>>> @@ -1329,6 +1329,12 @@ static int intel_pmu_hw_config(struct perf_event *event)
>>>> */
>>>> u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
>>>>
>>>> + /*
>>>> + * SNB introduced INST_RETIRED.PREC_DIST for this purpose.
>>>> + */
>>>> + if (x86_pmu.pebs_constraints == intel_snb_pebs_event_constraints)
>>>> + alt_config = X86_CONFIG(.event=0xc0, .umask=0x01,
>>>> + .inv=1, .cmask=16);
>>>>
>>>> alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
>>>> event->hw.config = alt_config;
>>>
>>> That's rather ugly.. but that's okay, I've actually got the patch for
>>> this still laying around, it needs a bit of an update though.
>>>
>> You cannot simply use PREC_DIST. This umask has some severe
>> restriction. When you measure it, NO other event on the the entire PMU
>> can be measured at the same time. It needs exclusive mode on SNB.
>>
>
> Yeah, I read something like above on the SDM. But just got confused with
> this:
>
> $ ./perf stat -e cycles:p,instructions,cache-references,cache-misses noploop 1
>
Passing :p in counting mode is useless, it does not do anything.
The :p suffix is only meaningful is sampling mode where it enables PEBS.
> Performance counter stats for 'noploop 1':
>
> 3,741,658,837 cycles # 0.000 GHz
> 3,618,983,116 instructions # 0.97 insns per cycle
> 51,126 cache-references
> 7,357 cache-misses # 14.390 % of all cache refs
>
> 1.000692634 seconds time elapsed
>
>
> Thanks,
> Namhyung
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