linux-kernel - Re: [PATCH v7 8/8] x86/tlb: just do tlb flush on one of siblings of SMT

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <4FBE4671.2090408@intel.com>
Date:	Thu, 24 May 2012 22:32:17 +0800
From:	Alex Shi <alex.shi@...el.com>
To:	Arjan van de Ven <arjan@...ux.intel.com>
CC:	Peter Zijlstra <peterz@...radead.org>,
	Andrew Lutomirski <luto@....edu>,
	Jan Beulich <JBeulich@...e.com>, borislav.petkov@....com,
	arnd@...db.de, akinobu.mita@...il.com, eric.dumazet@...il.com,
	fweisbec@...il.com, rostedt@...dmis.org, hughd@...gle.com,
	jeremy@...p.org, len.brown@...el.com, tony.luck@...el.com,
	yongjie.ren@...el.com, kamezawa.hiroyu@...fujitsu.com,
	seto.hidetoshi@...fujitsu.com, penberg@...nel.org,
	yinghai@...nel.org, tglx@...utronix.de, akpm@...ux-foundation.org,
	ak@...ux.intel.com, avi@...hat.com, dhowells@...hat.com,
	mingo@...hat.com, riel@...hat.com, cpw@....com, steiner@....com,
	linux-kernel@...r.kernel.org, viro@...iv.linux.org.uk,
	hpa@...or.com,
	"asit.k.mallick@...el.com" <asit.k.mallick@...el.com>
Subject: Re: [PATCH v7 8/8] x86/tlb: just do tlb flush on one of siblings
 of SMT

>>> we really really shouldn't do flushing of tlb's on only one half of SMT.

>>> SMT sibblings have their own TLB pool at least on some of Intels chips.
>>
>>
>> That is also the biggest question I want to know. Actually, some
>> documents, wiki said the SMT sibling just has process registers and
>> interrupt part, no any tlb/l1 cache etc, (like intel's doc
>> vol6iss1_hyper_threading_technology.pdf).  And the patch runs well on
>> NHM EP/WSM EP/NHM EX/SNB EP CPUs.
>>
>> But hard to get such clearly per cpu info of SMT/HT, so, what the
>> detailed Intel chips has 'TLB pool' on SMT?
> 
> all of them.
> 
> the TLB pool is shared as physical resource (dynamic or static, that
> depends), but each tlb entry will be tagged for which of the two HT
> pairs it's for, and on a logical level, they are completely separate as
> a result (as they should be)


But, why just flush part of SMT doesn't crash kernel on many benchmarks
testing? Does it means flush tlb without PCID (doesn't enable in current
kernel) will flush both of 'TLB pool'?

Oh, lots of questions of the TLB pool details. :) Could you like share
the URL of related documents?


> 


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/