linux-kernel - Re: mc13xxx-core: kernel hangs after 'regmap

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Message-ID: <20120524163604.GM5361@opensource.wolfsonmicro.com>
Date:	Thu, 24 May 2012 17:36:05 +0100
From:	Mark Brown <broonie@...nsource.wolfsonmicro.com>
To:	Philippe Rétornaz <philippe.retornaz@...l.ch>
Cc:	marc@...esign.com.au, Fabio Estevam <festevam@...il.com>,
	Shawn Guo <shawn.guo@...escale.com>,
	Uwe Kleine-König 
	<u.kleine-koenig@...gutronix.de>,
	Samuel Ortiz <sameo@...ux.intel.com>,
	Sascha Hauer <kernel@...gutronix.de>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: mc13xxx-core: kernel hangs after 'regmap_read'

On Thu, May 24, 2012 at 06:16:50PM +0200, Philippe Rétornaz wrote:

> Well, I think I found out why it's not working on mc13783.
> With regmap, each transfert is done with 8bits words. The SPI hardware assert 
> the SS signal only during 8 bits "register" transfert then deassert the SS. 
> Then the SS is asserted and 24bits (3 bytes) are transfered (datas).
> This clearly violate the datasheet which say SS must be asserted for the 
> *whole* transfert: register + data.

> This is why the old code used a 32bits word transfert, it ensured that the SPI 
> hardware was keeping SS asserted without interruptions.

> Is there any way to tell regmap to use 32bits transfert with the following 
> configuration (or doing it in a single shot 4x8bits):

I think this is just a plain bug in the SPI controller driver.  I think
I have seen it before in some FSL BSPs (I do remember having to fall
back to the bitbanging driver), it's surprising that it's also present
in the mainline driver so perhaps it's something different.  The driver
is deasserting chip select between transfers but it should only do so at
the end of the message unless told otherwise by the caller setting
cs_change.  regmap-spi uses spi_write_then_read() which does a single
spi_message for the write and read parts of the transfer.

If this is actually the issue the usual fix for this if the SPI
controller hardware can't be persuaded to do the right thing is to put
the chip select pin in GPIO mode and manage it by hand, though looking
at the driver it appears it should be doingn that already.  If you
change to using the bitbanging SPI driver it should do the right thing
(but will obviously be hideously slow), that ought to be at least a good
reference for expected behaviour here.
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